From 0cf217ff7b21d2fdbe3554a6e72bb130ae7c7402 Mon Sep 17 00:00:00 2001
From: "brice.boisson" <brice.boisson@epita.fr>
Date: Sun, 26 Nov 2023 22:31:27 +0900
Subject: [PATCH] Add: test source code for branch instruction

---
 .../tb_risc_v_cpu/branch_instruction.S         | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 tb/test_source_code/tb_risc_v_cpu/branch_instruction.S

diff --git a/tb/test_source_code/tb_risc_v_cpu/branch_instruction.S b/tb/test_source_code/tb_risc_v_cpu/branch_instruction.S
new file mode 100644
index 0000000..e474390
--- /dev/null
+++ b/tb/test_source_code/tb_risc_v_cpu/branch_instruction.S
@@ -0,0 +1,18 @@
+/*
+ *  0:zero, 1:ra, 2:sp, 3:gp, 4:tp, 5:t0-2, 8:s0/fp
+ *  9:s1, 10:a0-7, 18:s2-11, 28:t3-6
+ *  beq, bne, blt, ble, bltu, bgeu
+ *  bgt, bge, beqz, bnez, blez, bgez, bltz, bgtz
+ */
+
+addi a0, zero, 0 # R[10]=0
+start:
+beq a0, zero, second
+addi a0, a0, 1 # R[10]=3
+second:
+bne a0, zero, end
+addi a0, a0, 2 # R[10]=2
+j start
+end:
+
+# R[10]=3