diff --git a/Makefile b/Makefile
index e69de29..6f943de 100644
--- a/Makefile
+++ b/Makefile
@@ -0,0 +1,14 @@
+all: simulation
+	$(MAKE) -C sim $@
+
+debug: simulation
+	$(MAKE) -C sim $@
+
+simulation:
+	./scripts/gen_simu_do.sh $(TARGET) $(WAVE)
+
+clean:
+	rm -rf sim/work
+	rm -rf sim/transcript
+	rm -rf sim/vsim.wlf
+	rm -rf sim/simu.do
diff --git a/rtl/alu.v b/rtl/alu.v
new file mode 100644
index 0000000..5ecee99
--- /dev/null
+++ b/rtl/alu.v
@@ -0,0 +1,6 @@
+module alu (S, A, B);
+    output [31:0] S;
+    input [31:0] A, B;
+
+    xor N[31:0] (S, A, B);
+endmodule
\ No newline at end of file
diff --git a/scripts/gen_simu_do.sh b/scripts/gen_simu_do.sh
new file mode 100755
index 0000000..09aecb4
--- /dev/null
+++ b/scripts/gen_simu_do.sh
@@ -0,0 +1,37 @@
+#! /bin/sh
+
+if [ $# -lt 1 ]; then
+    echo "Usage: $0 <file_name> [signal]"
+    exit 1
+fi
+
+FILE_NAME=$1
+
+echo 'puts "Simulation script for ModelSim"
+' > ./sim/simu.do
+
+# test if "$1".v and tb_"$1".v files exist
+if [ ! -f "rtl/""$FILE_NAME"".v" ]; then
+    echo "Error: $FILE_NAME.v file not found!"
+    exit 1
+fi
+if [ ! -f "tb/tb_""$FILE_NAME"".v" ]; then
+    echo "Error: tb_$FILE_NAME.v file not found!"
+    exit 1
+fi
+
+echo 'vlib work
+vlog ../rtl/*.v
+vlog ../tb/tb_'"$FILE_NAME"'.v
+' >> ./sim/simu.do
+
+echo 'vsim tb_'"$FILE_NAME"'
+add wave -radix unsigned *' >> ./sim/simu.do
+
+# loop through all arguments from $3
+
+echo 'run -all' >> ./sim/simu.do
+
+exit 0
+
+# CRC - Hamming Code
diff --git a/sim/Makefile b/sim/Makefile
index e69de29..e2fcacd 100644
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -0,0 +1,5 @@
+all:
+	vsim -c -do "do simu.do; quit -f"
+
+debug:
+	vsim -do "do simu.do"
\ No newline at end of file
diff --git a/tb/tb_alu.v b/tb/tb_alu.v
new file mode 100644
index 0000000..c07f90a
--- /dev/null
+++ b/tb/tb_alu.v
@@ -0,0 +1,3 @@
+module tb_alu (S);
+    output [31:0] S;
+endmodule
\ No newline at end of file
diff --git a/tb/risc-v_cpu_tb.v b/tb/tb_risc-v_cpu.v
similarity index 100%
rename from tb/risc-v_cpu_tb.v
rename to tb/tb_risc-v_cpu.v