From 1f9a8ceebfd03d9724b245d79b5bd61544a81578 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Mon, 20 Nov 2023 22:30:19 +0900 Subject: [PATCH] Add: first test --- tb/tb_risc_v_cpu-dyn.v | 8 ++------ tb/test_source_code/tb_riscv_cpu/test.S | 9 +++++++++ 2 files changed, 11 insertions(+), 6 deletions(-) create mode 100644 tb/test_source_code/tb_riscv_cpu/test.S diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index 064c549..abbd224 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -31,7 +31,7 @@ module tb_risc_v_cpu (); /* Loading Test From File */ /* Loading Binary File */ - bin_file_inputs = $fopen("/home/brice/Code/RISC-V_VERILOG/tb/test.bin", "r"); + bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r"); if (bin_file_inputs == 0) begin $display("data_file handle was NULL"); $finish; @@ -59,10 +59,6 @@ module tb_risc_v_cpu (); i = i + 4; end end - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[0], 8'b00000000) - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[1], 8'b11000101) - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[2], 8'b10000111) - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[3], 8'b10110011) for (i = 0; i < 100; i = i + 1) begin `next_cycle @@ -70,7 +66,7 @@ module tb_risc_v_cpu (); end // final test - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.memory.memory[0], 8'b00000000) + `assert_no_wait("FOR LOOP - REG[5]: 1", risc_v_cpu.registers_bank.registers[5], 32'b1010) `end_message end diff --git a/tb/test_source_code/tb_riscv_cpu/test.S b/tb/test_source_code/tb_riscv_cpu/test.S new file mode 100644 index 0000000..bc689e5 --- /dev/null +++ b/tb/test_source_code/tb_riscv_cpu/test.S @@ -0,0 +1,9 @@ +# t0 = 0 +li t0, 0 +li t2, 10 +loop_head: +bge t0, t2, loop_end +# Repeated code goes here +addi t0, t0, 1 +j loop_head +loop_end: \ No newline at end of file