From 298e14be54009f3ea48f80ba50d7f9ce8a50e1ef Mon Sep 17 00:00:00 2001
From: "brice.boisson" <brice.boisson@epita.fr>
Date: Wed, 25 Oct 2023 09:01:54 +0900
Subject: [PATCH] Fix: readme checkbox

---
 README.md | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index e9cf119..02539c0 100644
--- a/README.md
+++ b/README.md
@@ -1,8 +1,9 @@
 # RISC-V Verilog
 
 This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
+
 This CPU will implement the RV32I ISA, with the following goal:
-[] Single cycle RISC-V RVI32I CPU
-[] Multi cycle CPU
-[] Pipelining
-[] (Bonus) RISC-V privileged ISA
\ No newline at end of file
+- [] Single cycle RISC-V RVI32I CPU
+- [] Multi cycle CPU
+- [] Pipelining
+- [] (Bonus) RISC-V privileged ISA
\ No newline at end of file