diff --git a/README.md b/README.md
index 9e73e16..c209f64 100644
--- a/README.md
+++ b/README.md
@@ -13,10 +13,13 @@ This CPU will implement the RV32I ISA, with the following goals:
 Use the command : ```make TARGET=<test_bench>-<sub_test>```
 
 With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_<test_bench>` directory. \
-Example: `make TARGET=risc_v_cpu-test`
+Example: `make TARGET=risc_v_cpu-alu_instruction`
 
 You can remove the dash and `sub_test` argument to run only the non source code based test. \
 Example: `make TARGET=risc_v_cpu`
 
 Or use `all` as a `sub_test` to run all test associated to a `test_bench`. \
 Example: `make TARGET=risc_v_cpu-all`
+
+You can add the flag `debug` at the end of the command to open ModelSim interface. \
+Example: `make TARGET=risc_v_cpu-alu_instruction debug`