From 30650abce8257ffbb552e3b1b096686b7f43ee7d Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Mon, 4 Dec 2023 11:02:20 +0900 Subject: [PATCH] Rebase: add change in test from main in multi-cycle-branch --- rtl/module_alu.v | 22 ++++++ rtl/module_program_counter.v | 35 ++++++++++ rtl/module_registers_bank.v | 30 +++++++++ rtl/program_counter.v | 4 +- rtl/risc_v_cpu.v | 65 ++++++------------ tb/tb_registers_bank.v | 1 + tb/tb_risc_v_cpu.v | 126 +++++++++++++++++------------------ 7 files changed, 174 insertions(+), 109 deletions(-) create mode 100644 rtl/module_alu.v create mode 100644 rtl/module_program_counter.v create mode 100644 rtl/module_registers_bank.v diff --git a/rtl/module_alu.v b/rtl/module_alu.v new file mode 100644 index 0000000..0704221 --- /dev/null +++ b/rtl/module_alu.v @@ -0,0 +1,22 @@ +module module_alu (input src, + input [3:0] func, + input [31:0] reg_in_a, reg_in_b, imm, + output [31:0] out); + + wire [31:0] in_b; + + mux2_1 mux2_in_b ( + .in_1(reg_in_b), + .in_2(imm), + .sel(src), + .out(in_b) + ); + + alu alu ( + .in_a(reg_in_a), + .in_b(in_b), + .func(func), + .out(out) + ); + +endmodule diff --git a/rtl/module_program_counter.v b/rtl/module_program_counter.v new file mode 100644 index 0000000..20660b8 --- /dev/null +++ b/rtl/module_program_counter.v @@ -0,0 +1,35 @@ +module module_program_counter (input clock, reset, + input is_jmp, alu_not, + input [1:0] is_branch, + input [31:0] alu_out, imm, + output [31:0] addr); + + wire [1:0] sel_in; + wire [31:0] pc_addr, new_addr; + + mux2_1 #(2) mux2_pc_sel_branch ( + .in_1(is_branch), + .in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}), + .sel(is_jmp), + .out(sel_in) + ); + + mux4_1 mux4_pc_sel_in ( + .in_1(pc_addr + 4), + .in_2(pc_addr + imm), + .in_3(alu_out), + .in_4(0), + .sel(sel_in), + .out(new_addr) + ); + + program_counter program_counter ( + .clock(clock), + .reset(reset), + .new_addr(new_addr), + .pc_addr(pc_addr) + ); + + assign addr = pc_addr; + +endmodule diff --git a/rtl/module_registers_bank.v b/rtl/module_registers_bank.v new file mode 100644 index 0000000..93a0df5 --- /dev/null +++ b/rtl/module_registers_bank.v @@ -0,0 +1,30 @@ +module module_registers_bank (input clock, reset, we, + input [1:0] sel_data_in, + input [4:0] sel_in, sel_out_a, sel_out_b, + input [31:0] alu_out, mem_out, pc_addr, + output [31:0] data_out_a, data_out_b); + + wire [31:0] data_in; + + mux4_1 mux4_reg_sel_data_in ( + .in_1(alu_out), + .in_2(mem_out), + .in_3(pc_addr + 4), + .in_4(pc_addr + alu_out), + .sel(sel_data_in), + .out(data_in) + ); + + registers_bank registers_bank ( + .clock(clock), + .reset(reset), + .we(we), + .sel_in(sel_in), + .sel_out_a(sel_out_a), + .sel_out_b(sel_out_b), + .data_in(data_in), + .data_out_a(data_out_a), + .data_out_b(data_out_b) + ); + +endmodule diff --git a/rtl/program_counter.v b/rtl/program_counter.v index f647764..18546a0 100644 --- a/rtl/program_counter.v +++ b/rtl/program_counter.v @@ -1,12 +1,12 @@ module program_counter (input clock, reset, - input [31:0] pc_new_addr, + input [31:0] new_addr, output reg [31:0] pc_addr); always @ (posedge clock, posedge reset) begin if (reset == 1'b1) pc_addr <= 32'b0; else - pc_addr <= pc_new_addr; + pc_addr <= new_addr; end endmodule diff --git a/rtl/risc_v_cpu.v b/rtl/risc_v_cpu.v index faa66b8..e9b22dc 100644 --- a/rtl/risc_v_cpu.v +++ b/rtl/risc_v_cpu.v @@ -8,11 +8,11 @@ module risc_v_cpu (input clock, reset, wire reg_we; wire [1:0] reg_sel_data_in; wire [4:0] reg_sel_out_a, reg_sel_out_b, reg_sel_in; - wire [31:0] reg_data_out_a, reg_data_out_b, reg_data_in; + wire [31:0] reg_data_out_a, reg_data_out_b; wire alu_src, alu_not; wire [3:0] alu_func; - wire [31:0] alu_in_b, alu_out; + wire [31:0] alu_out; wire mem_we; wire [1:0] mem_func_in; @@ -20,8 +20,8 @@ module risc_v_cpu (input clock, reset, wire [31:0] mem_out; wire pc_is_jmp; - wire [1:0] pc_is_branch, pc_sel_in; - wire [31:0] pc_addr, pc_new_addr; + wire [1:0] pc_is_branch; + wire [31:0] pc_addr; decoder decoder ( .instruction(instruction), @@ -41,53 +41,39 @@ module risc_v_cpu (input clock, reset, .alu_not(alu_not) ); - registers_bank registers_bank ( + module_registers_bank module_registers_bank ( .clock(clock), .reset(reset), .we(reg_we), + .sel_data_in(reg_sel_data_in), .sel_in(reg_sel_in), .sel_out_a(reg_sel_out_a), .sel_out_b(reg_sel_out_b), - .data_in(reg_data_in), + .alu_out(alu_out), + .mem_out(mem_out), + .pc_addr(pc_addr), .data_out_a(reg_data_out_a), .data_out_b(reg_data_out_b) ); - mux2_1 mux2_alu_in_b ( - .in_1(reg_data_out_b), - .in_2(imm), - .sel(alu_src), - .out(alu_in_b) - ); - - alu alu ( - .in_a(reg_data_out_a), - .in_b(alu_in_b), + module_alu module_alu ( + .src(alu_src), .func(alu_func), + .reg_in_a(reg_data_out_a), + .reg_in_b(reg_data_out_b), + .imm(imm), .out(alu_out) ); - mux2_1 #(2) mux2_pc_sel_branch ( - .in_1(pc_is_branch), - .in_2({1'b0, (alu_not ? (alu_out == 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}), - .sel(pc_is_jmp), - .out(pc_sel_in) - ); - - mux4_1 mux4_pc_sel_in ( - .in_1(pc_addr + 4), - .in_2(pc_addr + imm), - .in_3(alu_out), - .in_4(0), - .sel(pc_sel_in), - .out(pc_new_addr) - ); - - program_counter program_counter ( + module_program_counter module_program_counter ( .clock(clock), .reset(reset), - .pc_new_addr(pc_new_addr), - .pc_addr(pc_addr) + .is_jmp(pc_is_jmp), + .is_branch(pc_is_branch), + .alu_not(alu_not), + .alu_out(alu_out), + .imm(imm), + .addr(pc_addr) ); instruction uut_instruction ( @@ -106,13 +92,4 @@ module risc_v_cpu (input clock, reset, .data_out(mem_out) ); - mux4_1 mux4_reg_sel_data_in ( - .in_1(alu_out), - .in_2(mem_out), - .in_3(pc_addr + 4), - .in_4(pc_addr + alu_out), - .sel(reg_sel_data_in), - .out(reg_data_in) - ); - endmodule diff --git a/tb/tb_registers_bank.v b/tb/tb_registers_bank.v index c9115f5..9c00ed3 100644 --- a/tb/tb_registers_bank.v +++ b/tb/tb_registers_bank.v @@ -5,6 +5,7 @@ module tb_registers_bank (); integer i; reg clk; reg reset; + integer i; reg we; reg [4:0] sel_in; reg [4:0] sel_out_a; diff --git a/tb/tb_risc_v_cpu.v b/tb/tb_risc_v_cpu.v index 2b4485a..1177f07 100644 --- a/tb/tb_risc_v_cpu.v +++ b/tb/tb_risc_v_cpu.v @@ -66,117 +66,117 @@ module tb_risc_v_cpu (); risc_v_cpu.uut_instruction.memory[23] = 8'b11111111; `next_cycle - `assert_no_wait("FIBO INIT: ADDi $1, R[0], R[6] - R[6] = 1", risc_v_cpu.registers_bank.registers[6], 1) + `assert_no_wait("FIBO INIT: ADDi $1, R[0], R[6] - R[6] = 1", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 1) `next_cycle - `assert_no_wait("FIBO INIT: ADDi $0, R[0], R[7] - R[7] = 0", risc_v_cpu.registers_bank.registers[7], 0) + `assert_no_wait("FIBO INIT: ADDi $0, R[0], R[7] - R[7] = 0", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 0) `next_cycle - `assert_no_wait("FIBO CYCLE 1: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 1) + `assert_no_wait("FIBO CYCLE 1: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 1) `next_cycle - `assert_no_wait("FIBO CYCLE 1: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 1) + `assert_no_wait("FIBO CYCLE 1: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 1) `next_cycle - `assert_no_wait("FIBO CYCLE 1: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 1) + `assert_no_wait("FIBO CYCLE 1: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1) `next_cycle - `assert_no_wait("FIBO VALUE 1: 1", risc_v_cpu.registers_bank.registers[7], 1) - `assert_no_wait("FIBO CYCLE 1: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 1: 1", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1) + `assert_no_wait("FIBO CYCLE 1: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 2: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 1) + `assert_no_wait("FIBO CYCLE 2: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 1) `next_cycle - `assert_no_wait("FIBO CYCLE 2: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 2) + `assert_no_wait("FIBO CYCLE 2: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 2) `next_cycle - `assert_no_wait("FIBO CYCLE 2: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 1) + `assert_no_wait("FIBO CYCLE 2: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1) `next_cycle - `assert_no_wait("FIBO VALUE 2: 1", risc_v_cpu.registers_bank.registers[7], 1) - `assert_no_wait("FIBO CYCLE 2: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 2: 1", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1) + `assert_no_wait("FIBO CYCLE 2: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 3: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 2) + `assert_no_wait("FIBO CYCLE 3: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 2) `next_cycle - `assert_no_wait("FIBO CYCLE 3: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 3) + `assert_no_wait("FIBO CYCLE 3: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 3) `next_cycle - `assert_no_wait("FIBO CYCLE 3: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 2) + `assert_no_wait("FIBO CYCLE 3: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 2) `next_cycle - `assert_no_wait("FIBO VALUE 3: 2", risc_v_cpu.registers_bank.registers[7], 2) - `assert_no_wait("FIBO CYCLE 3: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 3: 2", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 2) + `assert_no_wait("FIBO CYCLE 3: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 4: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 3) + `assert_no_wait("FIBO CYCLE 4: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 3) `next_cycle - `assert_no_wait("FIBO CYCLE 4: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 5) + `assert_no_wait("FIBO CYCLE 4: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 5) `next_cycle - `assert_no_wait("FIBO CYCLE 4: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 3) + `assert_no_wait("FIBO CYCLE 4: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 3) `next_cycle - `assert_no_wait("FIBO VALUE 4: 3", risc_v_cpu.registers_bank.registers[7], 3) - `assert_no_wait("FIBO CYCLE 4: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 4: 3", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 3) + `assert_no_wait("FIBO CYCLE 4: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 5: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 5) + `assert_no_wait("FIBO CYCLE 5: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 5) `next_cycle - `assert_no_wait("FIBO CYCLE 5: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 8) + `assert_no_wait("FIBO CYCLE 5: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 8) `next_cycle - `assert_no_wait("FIBO CYCLE 5: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 5) + `assert_no_wait("FIBO CYCLE 5: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 5) `next_cycle - `assert_no_wait("FIBO VALUE 5: 5", risc_v_cpu.registers_bank.registers[7], 5) - `assert_no_wait("FIBO CYCLE 5: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 5: 5", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 5) + `assert_no_wait("FIBO CYCLE 5: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 6: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 8) + `assert_no_wait("FIBO CYCLE 6: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 8) `next_cycle - `assert_no_wait("FIBO CYCLE 6: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 13) + `assert_no_wait("FIBO CYCLE 6: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 13) `next_cycle - `assert_no_wait("FIBO CYCLE 6: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 8) + `assert_no_wait("FIBO CYCLE 6: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 8) `next_cycle - `assert_no_wait("FIBO VALUE 6: 8", risc_v_cpu.registers_bank.registers[7], 8) - `assert_no_wait("FIBO CYCLE 6: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 6: 8", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 8) + `assert_no_wait("FIBO CYCLE 6: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 7: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 13) + `assert_no_wait("FIBO CYCLE 7: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 13) `next_cycle - `assert_no_wait("FIBO CYCLE 7: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 21) + `assert_no_wait("FIBO CYCLE 7: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 21) `next_cycle - `assert_no_wait("FIBO CYCLE 7: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 13) + `assert_no_wait("FIBO CYCLE 7: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 13) `next_cycle - `assert_no_wait("FIBO VALUE 7: 13", risc_v_cpu.registers_bank.registers[7], 13) - `assert_no_wait("FIBO CYCLE 7: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 7: 13", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 13) + `assert_no_wait("FIBO CYCLE 7: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 8: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 21) + `assert_no_wait("FIBO CYCLE 8: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 21) `next_cycle - `assert_no_wait("FIBO CYCLE 8: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 34) + `assert_no_wait("FIBO CYCLE 8: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 34) `next_cycle - `assert_no_wait("FIBO CYCLE 8: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 21) + `assert_no_wait("FIBO CYCLE 8: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 21) `next_cycle - `assert_no_wait("FIBO VALUE 8: 21", risc_v_cpu.registers_bank.registers[7], 21) - `assert_no_wait("FIBO CYCLE 8: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 8: 21", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 21) + `assert_no_wait("FIBO CYCLE 8: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 9: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 34) + `assert_no_wait("FIBO CYCLE 9: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 34) `next_cycle - `assert_no_wait("FIBO CYCLE 9: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 55) + `assert_no_wait("FIBO CYCLE 9: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 55) `next_cycle - `assert_no_wait("FIBO CYCLE 9: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 34) + `assert_no_wait("FIBO CYCLE 9: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 34) `next_cycle - `assert_no_wait("FIBO VALUE 9: 34", risc_v_cpu.registers_bank.registers[7], 34) - `assert_no_wait("FIBO CYCLE 9: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 9: 34", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 34) + `assert_no_wait("FIBO CYCLE 9: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 10: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 55) + `assert_no_wait("FIBO CYCLE 10: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 55) `next_cycle - `assert_no_wait("FIBO CYCLE 10: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 89) + `assert_no_wait("FIBO CYCLE 10: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 89) `next_cycle - `assert_no_wait("FIBO CYCLE 10: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 55) + `assert_no_wait("FIBO CYCLE 10: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 55) `next_cycle - `assert_no_wait("FIBO VALUE 10: 55", risc_v_cpu.registers_bank.registers[7], 55) - `assert_no_wait("FIBO CYCLE 10: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 10: 55", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 55) + `assert_no_wait("FIBO CYCLE 10: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 11: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 89) + `assert_no_wait("FIBO CYCLE 11: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 89) `next_cycle - `assert_no_wait("FIBO CYCLE 11: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 144) + `assert_no_wait("FIBO CYCLE 11: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 144) `next_cycle - `assert_no_wait("FIBO CYCLE 11: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 89) + `assert_no_wait("FIBO CYCLE 11: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 89) `next_cycle - `assert_no_wait("FIBO VALUE 11: 89", risc_v_cpu.registers_bank.registers[7], 89) - `assert_no_wait("FIBO CYCLE 11: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 11: 89", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 89) + `assert_no_wait("FIBO CYCLE 11: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) `next_cycle - `assert_no_wait("FIBO CYCLE 12: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 144) + `assert_no_wait("FIBO CYCLE 12: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 144) `next_cycle - `assert_no_wait("FIBO CYCLE 12: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 233) + `assert_no_wait("FIBO CYCLE 12: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 233) `next_cycle - `assert_no_wait("FIBO CYCLE 12: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 144) + `assert_no_wait("FIBO CYCLE 12: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 144) `next_cycle - `assert_no_wait("FIBO VALUE 12: 144", risc_v_cpu.registers_bank.registers[7], 144) - `assert_no_wait("FIBO CYCLE 12: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8) + `assert_no_wait("FIBO VALUE 12: 144", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 144) + `assert_no_wait("FIBO CYCLE 12: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8) /* Reset */ reset = 1'b1; @@ -339,7 +339,7 @@ module tb_risc_v_cpu (); `assert_no_wait("BUBBLE SORT - MEM[7]: 8", risc_v_cpu.memory.memory[7], 8) `assert_no_wait("BUBBLE SORT - MEM[8]: 9", risc_v_cpu.memory.memory[8], 9) `assert_no_wait("BUBBLE SORT - MEM[9]: 10", risc_v_cpu.memory.memory[9], 10) - `assert_no_wait("BUBBLE SORT - PROGRAM EXITED - PC: 76", risc_v_cpu.program_counter.pc_addr, 76) + `assert_no_wait("BUBBLE SORT - PROGRAM EXITED - PC: 76", risc_v_cpu.module_program_counter.program_counter.pc_addr, 76) `end_message end