From 3eb7603cd00e2058e408c574b242df7493dc1f56 Mon Sep 17 00:00:00 2001
From: "brice.boisson" <brice.boisson@epita.fr>
Date: Wed, 25 Oct 2023 09:00:42 +0900
Subject: [PATCH] Add: new infos in the readme

---
 README.md | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/README.md b/README.md
index 9cda1f5..e9cf119 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,8 @@
+# RISC-V Verilog
+
 This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
+This CPU will implement the RV32I ISA, with the following goal:
+[] Single cycle RISC-V RVI32I CPU
+[] Multi cycle CPU
+[] Pipelining
+[] (Bonus) RISC-V privileged ISA
\ No newline at end of file