From 4ded2be172412423676ca4cf31e6c01745b6ef67 Mon Sep 17 00:00:00 2001
From: "brice.boisson" <brice.boisson@epita.fr>
Date: Tue, 10 Oct 2023 16:17:16 +0900
Subject: [PATCH] Add: README

---
 .gitignore | 0
 README.md  | 1 +
 2 files changed, 1 insertion(+)
 create mode 100644 .gitignore

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/README.md b/README.md
index e69de29..9cda1f5 100644
--- a/README.md
+++ b/README.md
@@ -0,0 +1 @@
+This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.