From 5d35edeb63908605adf9cebb601069a1514114c2 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Mon, 4 Dec 2023 11:16:24 +0900 Subject: [PATCH] Rebase: fix merge issue --- rtl/module_program_counter.v | 2 +- tb/tb_registers_bank.v | 1 - tb/tb_risc_v_cpu-dyn.v | 8 ++++---- tb/tb_tools.vh | 4 ++-- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/rtl/module_program_counter.v b/rtl/module_program_counter.v index 20660b8..b0f724b 100644 --- a/rtl/module_program_counter.v +++ b/rtl/module_program_counter.v @@ -9,7 +9,7 @@ module module_program_counter (input clock, reset, mux2_1 #(2) mux2_pc_sel_branch ( .in_1(is_branch), - .in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}), + .in_2({1'b0, (alu_not ? (alu_out == 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}), .sel(is_jmp), .out(sel_in) ); diff --git a/tb/tb_registers_bank.v b/tb/tb_registers_bank.v index 9c00ed3..c9115f5 100644 --- a/tb/tb_registers_bank.v +++ b/tb/tb_registers_bank.v @@ -5,7 +5,6 @@ module tb_registers_bank (); integer i; reg clk; reg reset; - integer i; reg we; reg [4:0] sel_in; reg [4:0] sel_out_a; diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index 9520fd1..16d3421 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -112,8 +112,8 @@ module tb_risc_v_cpu (); /* Run The Program */ for (i = 0; i < 10000; i = i + 1) begin - if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin - curent_addr = risc_v_cpu.program_counter.pc_addr / 4; + if (test[risc_v_cpu.module_program_counter.program_counter.pc_addr / 4][5:0] != 6'b111111) begin + curent_addr = risc_v_cpu.module_program_counter.program_counter.pc_addr / 4; `next_cycle /* Test State During Execution */ @@ -151,9 +151,9 @@ module tb_risc_v_cpu (); /* Test State After Execution */ if (reg_number < 6'b100000) begin - `assert_no_wait_reg("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.registers_bank.registers[reg_number[4:0]]) + `assert_no_wait_reg("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.module_registers_bank.registers_bank.registers[reg_number[4:0]]) end else if (reg_number == 6'b100000) begin - `assert_no_wait_pc("FINAL", 1'bx, reg_test_value, risc_v_cpu.program_counter.pc_addr) + `assert_no_wait_pc("FINAL", 1'bx, reg_test_value, risc_v_cpu.module_program_counter.program_counter.pc_addr) end else if (reg_number > 6'b100000) begin `assert_no_wait_mem("FINAL", 1'bx, reg_number - 6'b100001, reg_test_value, {risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4 + 3], risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4 + 2], risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4 + 1], risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4]}) end diff --git a/tb/tb_tools.vh b/tb/tb_tools.vh index 936fba1..eb758dd 100644 --- a/tb/tb_tools.vh +++ b/tb/tb_tools.vh @@ -31,9 +31,9 @@ `define test_result(message, curent_addr, addr_range, test_range) \ if (test[curent_addr][addr_range:addr_range - 5] < 6'b100000) begin \ - `assert_no_wait_reg(message, curent_addr, test[curent_addr][addr_range:addr_range - 5], test[curent_addr][test_range:test_range - 31], risc_v_cpu.registers_bank.registers[test[curent_addr][addr_range - 1:addr_range - 5]]) \ + `assert_no_wait_reg(message, curent_addr, test[curent_addr][addr_range:addr_range - 5], test[curent_addr][test_range:test_range - 31], risc_v_cpu.module_registers_bank.registers_bank.registers[test[curent_addr][addr_range - 1:addr_range - 5]]) \ end else if (test[curent_addr][addr_range:addr_range - 5] == 6'b100000) begin \ - `assert_no_wait_pc(message, curent_addr, test[curent_addr][test_range:test_range - 31], risc_v_cpu.program_counter.pc_addr) \ + `assert_no_wait_pc(message, curent_addr, test[curent_addr][test_range:test_range - 31], risc_v_cpu.module_program_counter.program_counter.pc_addr) \ end else if (test[curent_addr][addr_range:addr_range - 5] > 6'b100000) begin \ `assert_no_wait_mem(message, curent_addr, test[curent_addr][addr_range:addr_range - 5] - 6'b100001, test[curent_addr][test_range:test_range - 31], {risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4 + 3], risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4 + 2], risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4 + 1], risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4]}) \ end