From 86abae02ebbe0767d1a5ec62e27bc4c551867c57 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Sat, 25 Nov 2023 19:28:17 +0900 Subject: [PATCH] Add: name of the dynamic test following the tested element --- tb/tb_risc_v_cpu-dyn.v | 26 ++++++++++++++------------ tb/tb_tools.vh | 22 ++++++++++++++++++++-- 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index 6c3b850..b225657 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -22,6 +22,8 @@ module tb_risc_v_cpu (); integer curent_addr; integer res; reg [8:0] dump; + reg [50*8:1] message; + integer size; risc_v_cpu risc_v_cpu ( .clock(clk), @@ -113,29 +115,29 @@ module tb_risc_v_cpu (); `next_cycle if (test[curent_addr][5:0] != 6'b111111) begin if (test[curent_addr][5:0] < 6'b100000) begin - `assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]], test[curent_addr][37:6]) + `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]], test[curent_addr][37:6]) end else if (test[curent_addr][5:0] == 6'b100000) begin - `assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][37:6]) + `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][37:6]) end else if (test[curent_addr][5:0] > 6'b100000) begin - `assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][5:0]], test[curent_addr][37:6]) + `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.memory.memory[test[curent_addr][5:0]], test[curent_addr][37:6]) end end if (test[curent_addr][43:38] != 6'b111111) begin if (test[curent_addr][43:38] < 6'b100000) begin - `assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]], test[curent_addr][75:44]) + `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]], test[curent_addr][75:44]) end else if (test[curent_addr][43:38] == 6'b100000) begin - `assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][75:44]) + `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][75:44]) end else if (test[curent_addr][43:38] > 6'b100000) begin - `assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][43:38]], test[curent_addr][75:44]) + `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.memory.memory[test[curent_addr][43:38]], test[curent_addr][75:44]) end end if (test[curent_addr][81:76] != 6'b111111) begin if (test[curent_addr][81:76] < 6'b100000) begin - `assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]], test[curent_addr][81:76]) + `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]], test[curent_addr][81:76]) end else if (test[curent_addr][81:76] == 6'b100000) begin - `assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][113:83]) + `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][113:83]) end else if (test[curent_addr][81:76] > 6'b100000) begin - `assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][81:76]], test[curent_addr][81:76]) + `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]], test[curent_addr][81:76]) end end end @@ -159,11 +161,11 @@ module tb_risc_v_cpu (); end if (reg_number < 6'b100000) begin - `assert_no_wait("FINAL TEST - REG", risc_v_cpu.registers_bank.registers[reg_number[4:0]], reg_test_value) + `assert_no_wait_reg("FINAL", 1'bx, reg_number, risc_v_cpu.registers_bank.registers[reg_number[4:0]], reg_test_value) end else if (reg_number == 6'b100000) begin - `assert_no_wait("FINAL TEST- PC", risc_v_cpu.program_counter.pc_addr, reg_test_value) + `assert_no_wait_pc("FINAL", 1'bx, risc_v_cpu.program_counter.pc_addr, reg_test_value) end else if (reg_number > 6'b100000) begin - `assert_no_wait("FINAL TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][5:0]], reg_test_value) + `assert_no_wait_mem("FINAL", 1'bx, reg_number, risc_v_cpu.memory.memory[test[curent_addr][5:0]], reg_test_value) end end diff --git a/tb/tb_tools.vh b/tb/tb_tools.vh index 7e5a593..1a8b416 100644 --- a/tb/tb_tools.vh +++ b/tb/tb_tools.vh @@ -1,16 +1,34 @@ `define assert(message, expected, got) \ #4 \ if(expected !== got) begin \ - $display("\033[0;31m[FAIL]\033[0m %s - got: %d, expected: %d", message, expected, got); \ + $display("\033[0;31m[FAIL]\033[0m %s - got: %0d, expected: %0d", message, expected, got); \ end else \ $display("\033[0;32m[PASS]\033[0m %s", message); `define assert_no_wait(message, expected, got) \ if(expected !== got) begin \ - $display("\033[0;31m[FAIL]\033[0m %s - got: %d, expected: %d", message, expected, got); \ + $display("\033[0;31m[FAIL]\033[0m %s - got: %0d, expected: %0d", message, expected, got); \ end else \ $display("\033[0;32m[PASS]\033[0m %s", message); +`define assert_no_wait_reg(message, instr_addr, reg_addr, expected, got) \ + if(expected !== got) begin \ + $display("\033[0;31m[FAIL]\033[0m %s - INSTR: %0d - REG[%0d] = %0d, got: %0d", message, instr_addr, reg_addr, expected, got); \ + end else \ + $display("\033[0;32m[PASS]\033[0m %s - INSTR: %0d - REG[%0d] = %0d", message, instr_addr, reg_addr, expected); + +`define assert_no_wait_pc(message, instr_addr, expected, got) \ + if(expected !== got) begin \ + $display("\033[0;31m[FAIL]\033[0m %s - INSTR: %0d - PC = %0d, got: %0d", message, instr_addr, expected, got); \ + end else \ + $display("\033[0;32m[PASS]\033[0m %s - INSTR: %0d - PC = %0d", message, instr_addr, expected); + +`define assert_no_wait_mem(message, instr_addr, mem_addr, expected, got) \ + if(expected !== got) begin \ + $display("\033[0;31m[FAIL]\033[0m %s - INSTR: %0d - MEM[%0d] = %0d, got: %0d", message, instr_addr, mem_addr, expected, got); \ + end else \ + $display("\033[0;32m[PASS]\033[0m %s - INSTR: %0d - MEM[%0d] = %0d", message, instr_addr, mem_addr, expected); + `define end_message $display("\033[0;32mIf no \033[0mFAIL\033[0;32m messages, all tests passed!\033[0m"); `define next_cycle \