From 93cb91f02287c568ab31f1bebc998ed9b1739081 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Mon, 20 Nov 2023 14:21:26 +0900 Subject: [PATCH] Add: script --- scripts/gen_simu_do.sh | 9 ++--- scripts/get_bin.sh | 21 ++++++++++++ tb/tb_risc_v_cpu-dyn.v | 77 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+), 4 deletions(-) create mode 100755 scripts/get_bin.sh create mode 100644 tb/tb_risc_v_cpu-dyn.v diff --git a/scripts/gen_simu_do.sh b/scripts/gen_simu_do.sh index 7991609..56fb1cb 100755 --- a/scripts/gen_simu_do.sh +++ b/scripts/gen_simu_do.sh @@ -5,7 +5,8 @@ if [ $# -lt 1 ]; then exit 1 fi -FILE_NAME=$1 +TB_FILE_NAME=tb_$1 +FILE_NAME=$(echo "$1" | sed 's/\([[:alnum:]_]*\)[-.].*/\1/') echo 'puts "Simulation script for ModelSim" ' > ./sim/simu.do @@ -15,14 +16,14 @@ if [ ! -f "rtl/""$FILE_NAME"".v" ]; then echo "Error: $FILE_NAME.v file not found!" exit 1 fi -if [ ! -f "tb/tb_""$FILE_NAME"".v" ]; then - echo "Error: tb_$FILE_NAME.v file not found!" +if [ ! -f "tb/""$TB_FILE_NAME"".v" ]; then + echo "Error: ""$TB_FILE_NAME"".v file not found!" exit 1 fi echo 'vlib work vlog ../rtl/*.v -vlog ../tb/tb_'"$FILE_NAME"'.v +vlog ../tb/'"$TB_FILE_NAME"'.v ' >> ./sim/simu.do echo 'vsim tb_'"$FILE_NAME"' diff --git a/scripts/get_bin.sh b/scripts/get_bin.sh new file mode 100755 index 0000000..9c4c331 --- /dev/null +++ b/scripts/get_bin.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +if [ ! command -v riscv32-unknown-elf-as &> /dev/null ] \ + || [ ! command -v riscv32-unknown-elf-ld &> /dev/null ] \ + || [ ! command -v riscv32-unknown-elf-objcopy &> /dev/null ] +then + echo "riscv32-unknown-elf could not be found" + exit 1 +fi + +if [ $# -eq 0 ] +then + echo "Usage: $0 " + exit 1 +fi + +NAME=$1 + +riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${NAME}.S -o ${NAME}.o +riscv32-unknown-elf-ld -Ttext=0x1000 ${NAME}.o -o ${NAME}.elf +riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v new file mode 100644 index 0000000..d226e85 --- /dev/null +++ b/tb/tb_risc_v_cpu-dyn.v @@ -0,0 +1,77 @@ +`timescale 1ns / 1ps +`include "tb_tools.vh" + +module tb_risc_v_cpu (); + reg clk; + reg reset; + integer i; + wire [31:0] out; + + /* File management variable */ + integer bin_file_inputs; + reg [8:0] read_instruction_1; + reg [8:0] read_instruction_2; + reg [8:0] read_instruction_3; + reg [8:0] read_instruction_4; + + risc_v_cpu risc_v_cpu ( + .clock(clk), + .reset(reset), + .out(out) + ); + + initial begin + /* Reset */ + reset = 1'b1; + #10 + reset = 1'b0; + + clk = 1'b0; + + /* Loading Test From File */ + + /* Loading Binary File */ + bin_file_inputs = $fopen("/home/brice/Code/RISC-V_VERILOG/tb/test.bin", "r"); + if (bin_file_inputs == 0) begin + $display("data_file handle was NULL"); + $finish; + end + + i = 0; + while (!$feof(bin_file_inputs)) + begin + read_instruction_1 = $fgetc(bin_file_inputs); + read_instruction_2 = $fgetc(bin_file_inputs); + read_instruction_3 = $fgetc(bin_file_inputs); + read_instruction_4 = $fgetc(bin_file_inputs); + + if ( + read_instruction_1[8] != 1'b1 && + read_instruction_2[8] != 1'b1 && + read_instruction_3[8] != 1'b1 && + read_instruction_4[8] != 1'b1 + ) begin + risc_v_cpu.uut_instruction.memory[i] = read_instruction_4[7:0]; + risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_3[7:0]; + risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_2[7:0]; + risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_1[7:0]; + i = i + 4; + end + end + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[0], 8'b00000000) + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[1], 8'b11000101) + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[2], 8'b10000111) + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[3], 8'b10110011) + + for (i = 0; i < 1; i = i + 1) begin + `next_cycle + // run + end + + // final test + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.memory.memory[0], 8'b00000000) + + `end_message + end + +endmodule : tb_risc_v_cpu