From 9c151ccbb232385391f7f486909712bc941abd29 Mon Sep 17 00:00:00 2001
From: "brice.boisson" <brice.boisson@epita.fr>
Date: Wed, 25 Oct 2023 09:02:19 +0900
Subject: [PATCH] Fix: readme checkbox 2

---
 README.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index 02539c0..6c06be3 100644
--- a/README.md
+++ b/README.md
@@ -3,7 +3,7 @@
 This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
 
 This CPU will implement the RV32I ISA, with the following goal:
-- [] Single cycle RISC-V RVI32I CPU
-- [] Multi cycle CPU
-- [] Pipelining
-- [] (Bonus) RISC-V privileged ISA
\ No newline at end of file
+- [ ] Single cycle RISC-V RVI32I CPU
+- [ ] Multi cycle CPU
+- [ ] Pipelining
+- [ ] (Bonus) RISC-V privileged ISA
\ No newline at end of file