From a15dc204e502fac24431f56649be40ce084675d4 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Wed, 25 Oct 2023 09:03:02 +0900 Subject: [PATCH] Fix: synthax --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 6c06be3..ce1d60a 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose. -This CPU will implement the RV32I ISA, with the following goal: +This CPU will implement the RV32I ISA, with the following goals: - [ ] Single cycle RISC-V RVI32I CPU - [ ] Multi cycle CPU - [ ] Pipelining