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 This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.
 
 This CPU will implement the RV32I ISA, with the following goals:
-- [ ] Single cycle RISC-V RVI32I CPU
+- [X] Single cycle RISC-V RVI32I CPU
 - [ ] Multi cycle CPU
 - [ ] Pipelining
 - [ ] (Bonus) RISC-V privileged ISA
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