From c6ffe7e2e922b338d4bbbab75c6b480f07cd012e Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Sun, 26 Nov 2023 22:22:16 +0900 Subject: [PATCH] Fix: dynamique test bench else cond --- tb/tb_risc_v_cpu-dyn.v | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index 58d5873..733d621 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -98,7 +98,6 @@ module tb_risc_v_cpu (); test[instruction_addr][5:0] = reg_number; test[instruction_addr][37:6] = reg_test_value; end else if (test[instruction_addr][43:38] == 6'b111111) begin - $display ("1"); test[instruction_addr][43:38] = reg_number; test[instruction_addr][75:44] = reg_test_value; end else if (test[instruction_addr][81:76] == 6'b111111) begin @@ -142,9 +141,9 @@ module tb_risc_v_cpu (); `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]]) end end - end - else + end else begin `next_cycle + end end /* Test State After Execution */