diff --git a/rtl/risc-v_cpu_top.v b/rtl/risc-v_cpu_top.v
deleted file mode 100644
index e69de29..0000000
diff --git a/rtl/risc_v_cpu_top.v b/rtl/risc_v_cpu_top.v
new file mode 100644
index 0000000..4148343
--- /dev/null
+++ b/rtl/risc_v_cpu_top.v
@@ -0,0 +1,13 @@
+module risc_v_cpu_top (input         clock, reset,
+                       output [31:0] out);
+
+    /* You can use the following file as your top layer for your FPGA synthesis */
+
+    risc_v_cpu risc_v_cpu (
+        .clock(clock),
+        .reset(reset),
+        .out(out)
+    );
+
+endmodule
+
diff --git a/tb/tb_registers_bank.v b/tb/tb_registers_bank.v
index d44bab0..c9115f5 100644
--- a/tb/tb_registers_bank.v
+++ b/tb/tb_registers_bank.v
@@ -2,6 +2,7 @@
 `include "tb_tools.vh"
 
 module tb_registers_bank ();
+    integer     i;
     reg         clk;
     reg         reset;
     reg         we;
diff --git a/tb/tb_tools.vh b/tb/tb_tools.vh
index 90f81c0..6479aa4 100644
--- a/tb/tb_tools.vh
+++ b/tb/tb_tools.vh
@@ -42,4 +42,4 @@
 
 `define next_cycle \
     #1 clk = ~clk; \
-    #1 clk = ~clk;
\ No newline at end of file
+    #1 clk = ~clk;