From 93cb91f02287c568ab31f1bebc998ed9b1739081 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Mon, 20 Nov 2023 14:21:26 +0900 Subject: [PATCH 1/3] Add: script --- scripts/gen_simu_do.sh | 9 ++--- scripts/get_bin.sh | 21 ++++++++++++ tb/tb_risc_v_cpu-dyn.v | 77 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+), 4 deletions(-) create mode 100755 scripts/get_bin.sh create mode 100644 tb/tb_risc_v_cpu-dyn.v diff --git a/scripts/gen_simu_do.sh b/scripts/gen_simu_do.sh index 7991609..56fb1cb 100755 --- a/scripts/gen_simu_do.sh +++ b/scripts/gen_simu_do.sh @@ -5,7 +5,8 @@ if [ $# -lt 1 ]; then exit 1 fi -FILE_NAME=$1 +TB_FILE_NAME=tb_$1 +FILE_NAME=$(echo "$1" | sed 's/\([[:alnum:]_]*\)[-.].*/\1/') echo 'puts "Simulation script for ModelSim" ' > ./sim/simu.do @@ -15,14 +16,14 @@ if [ ! -f "rtl/""$FILE_NAME"".v" ]; then echo "Error: $FILE_NAME.v file not found!" exit 1 fi -if [ ! -f "tb/tb_""$FILE_NAME"".v" ]; then - echo "Error: tb_$FILE_NAME.v file not found!" +if [ ! -f "tb/""$TB_FILE_NAME"".v" ]; then + echo "Error: ""$TB_FILE_NAME"".v file not found!" exit 1 fi echo 'vlib work vlog ../rtl/*.v -vlog ../tb/tb_'"$FILE_NAME"'.v +vlog ../tb/'"$TB_FILE_NAME"'.v ' >> ./sim/simu.do echo 'vsim tb_'"$FILE_NAME"' diff --git a/scripts/get_bin.sh b/scripts/get_bin.sh new file mode 100755 index 0000000..9c4c331 --- /dev/null +++ b/scripts/get_bin.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +if [ ! command -v riscv32-unknown-elf-as &> /dev/null ] \ + || [ ! command -v riscv32-unknown-elf-ld &> /dev/null ] \ + || [ ! command -v riscv32-unknown-elf-objcopy &> /dev/null ] +then + echo "riscv32-unknown-elf could not be found" + exit 1 +fi + +if [ $# -eq 0 ] +then + echo "Usage: $0 " + exit 1 +fi + +NAME=$1 + +riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${NAME}.S -o ${NAME}.o +riscv32-unknown-elf-ld -Ttext=0x1000 ${NAME}.o -o ${NAME}.elf +riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v new file mode 100644 index 0000000..d226e85 --- /dev/null +++ b/tb/tb_risc_v_cpu-dyn.v @@ -0,0 +1,77 @@ +`timescale 1ns / 1ps +`include "tb_tools.vh" + +module tb_risc_v_cpu (); + reg clk; + reg reset; + integer i; + wire [31:0] out; + + /* File management variable */ + integer bin_file_inputs; + reg [8:0] read_instruction_1; + reg [8:0] read_instruction_2; + reg [8:0] read_instruction_3; + reg [8:0] read_instruction_4; + + risc_v_cpu risc_v_cpu ( + .clock(clk), + .reset(reset), + .out(out) + ); + + initial begin + /* Reset */ + reset = 1'b1; + #10 + reset = 1'b0; + + clk = 1'b0; + + /* Loading Test From File */ + + /* Loading Binary File */ + bin_file_inputs = $fopen("/home/brice/Code/RISC-V_VERILOG/tb/test.bin", "r"); + if (bin_file_inputs == 0) begin + $display("data_file handle was NULL"); + $finish; + end + + i = 0; + while (!$feof(bin_file_inputs)) + begin + read_instruction_1 = $fgetc(bin_file_inputs); + read_instruction_2 = $fgetc(bin_file_inputs); + read_instruction_3 = $fgetc(bin_file_inputs); + read_instruction_4 = $fgetc(bin_file_inputs); + + if ( + read_instruction_1[8] != 1'b1 && + read_instruction_2[8] != 1'b1 && + read_instruction_3[8] != 1'b1 && + read_instruction_4[8] != 1'b1 + ) begin + risc_v_cpu.uut_instruction.memory[i] = read_instruction_4[7:0]; + risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_3[7:0]; + risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_2[7:0]; + risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_1[7:0]; + i = i + 4; + end + end + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[0], 8'b00000000) + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[1], 8'b11000101) + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[2], 8'b10000111) + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[3], 8'b10110011) + + for (i = 0; i < 1; i = i + 1) begin + `next_cycle + // run + end + + // final test + `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.memory.memory[0], 8'b00000000) + + `end_message + end + +endmodule : tb_risc_v_cpu From 99399cd9b3eb1f5ff7da1c0129f6ea37ff9c843d Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Mon, 20 Nov 2023 22:20:42 +0900 Subject: [PATCH 2/3] Add: test from gcc --- Makefile | 3 +++ rtl/decoder.v | 4 ++-- rtl/risc_v_cpu.v | 2 +- scripts/get_bin.sh | 4 +++- sim/Makefile | 1 + tb/tb_risc_v_cpu-dyn.v | 11 ++++++----- 6 files changed, 16 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 2d60956..0303bd2 100644 --- a/Makefile +++ b/Makefile @@ -14,3 +14,6 @@ clean: rm -rf transcript rm -rf sim/vsim.wlf rm -rf sim/simu.do + rm -rf tb/test_source_code/**/*.bin + rm -rf tb/test_source_code/**/*.elf + rm -rf tb/test_source_code/**/*.o diff --git a/rtl/decoder.v b/rtl/decoder.v index a5a8e20..00ab67b 100644 --- a/rtl/decoder.v +++ b/rtl/decoder.v @@ -147,7 +147,7 @@ endfunction alu_not = 0; end BRANCH : begin // BRANCH - Beq, ... - imm[11:0] = {instruction[31:25], instruction[11:7]}; + imm[11:0] = {instruction[7], instruction[30:25], instruction[11:8], 1'b0}; imm[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111; reg_we = 0; reg_sel_data_in = 2'b00; @@ -164,7 +164,7 @@ endfunction alu_not = branch_not(instruction[14:12]); end JAL : begin // JUMP - Jal - imm[19:0] = instruction[31:12]; + imm[19:0] = {instruction[31], instruction[19:12], instruction[20], instruction[30:25], instruction[24:21], 1'b0}; imm[31:20] = (instruction[31] == 0) ? 12'b000000000000 : 12'b111111111111; reg_we = 1; reg_sel_data_in = 2'b10; diff --git a/rtl/risc_v_cpu.v b/rtl/risc_v_cpu.v index 4614322..faa66b8 100644 --- a/rtl/risc_v_cpu.v +++ b/rtl/risc_v_cpu.v @@ -69,7 +69,7 @@ module risc_v_cpu (input clock, reset, mux2_1 #(2) mux2_pc_sel_branch ( .in_1(pc_is_branch), - .in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}), + .in_2({1'b0, (alu_not ? (alu_out == 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}), .sel(pc_is_jmp), .out(pc_sel_in) ); diff --git a/scripts/get_bin.sh b/scripts/get_bin.sh index 9c4c331..77729b6 100755 --- a/scripts/get_bin.sh +++ b/scripts/get_bin.sh @@ -17,5 +17,7 @@ fi NAME=$1 riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${NAME}.S -o ${NAME}.o -riscv32-unknown-elf-ld -Ttext=0x1000 ${NAME}.o -o ${NAME}.elf +riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin + +# rm -rf ${NAME}.o ${NAME}.elf diff --git a/sim/Makefile b/sim/Makefile index e2fcacd..1fdd80e 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,4 +1,5 @@ all: + ./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test vsim -c -do "do simu.do; quit -f" debug: diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index d226e85..064c549 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -44,6 +44,7 @@ module tb_risc_v_cpu (); read_instruction_2 = $fgetc(bin_file_inputs); read_instruction_3 = $fgetc(bin_file_inputs); read_instruction_4 = $fgetc(bin_file_inputs); + $display("read_instruction_1: %b", read_instruction_1); if ( read_instruction_1[8] != 1'b1 && @@ -51,10 +52,10 @@ module tb_risc_v_cpu (); read_instruction_3[8] != 1'b1 && read_instruction_4[8] != 1'b1 ) begin - risc_v_cpu.uut_instruction.memory[i] = read_instruction_4[7:0]; - risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_3[7:0]; - risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_2[7:0]; - risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_1[7:0]; + risc_v_cpu.uut_instruction.memory[i] = read_instruction_1[7:0]; + risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_2[7:0]; + risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_3[7:0]; + risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_4[7:0]; i = i + 4; end end @@ -63,7 +64,7 @@ module tb_risc_v_cpu (); `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[2], 8'b10000111) `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[3], 8'b10110011) - for (i = 0; i < 1; i = i + 1) begin + for (i = 0; i < 100; i = i + 1) begin `next_cycle // run end From 1f9a8ceebfd03d9724b245d79b5bd61544a81578 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Mon, 20 Nov 2023 22:30:19 +0900 Subject: [PATCH 3/3] Add: first test --- tb/tb_risc_v_cpu-dyn.v | 8 ++------ tb/test_source_code/tb_riscv_cpu/test.S | 9 +++++++++ 2 files changed, 11 insertions(+), 6 deletions(-) create mode 100644 tb/test_source_code/tb_riscv_cpu/test.S diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index 064c549..abbd224 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -31,7 +31,7 @@ module tb_risc_v_cpu (); /* Loading Test From File */ /* Loading Binary File */ - bin_file_inputs = $fopen("/home/brice/Code/RISC-V_VERILOG/tb/test.bin", "r"); + bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r"); if (bin_file_inputs == 0) begin $display("data_file handle was NULL"); $finish; @@ -59,10 +59,6 @@ module tb_risc_v_cpu (); i = i + 4; end end - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[0], 8'b00000000) - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[1], 8'b11000101) - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[2], 8'b10000111) - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[3], 8'b10110011) for (i = 0; i < 100; i = i + 1) begin `next_cycle @@ -70,7 +66,7 @@ module tb_risc_v_cpu (); end // final test - `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.memory.memory[0], 8'b00000000) + `assert_no_wait("FOR LOOP - REG[5]: 1", risc_v_cpu.registers_bank.registers[5], 32'b1010) `end_message end diff --git a/tb/test_source_code/tb_riscv_cpu/test.S b/tb/test_source_code/tb_riscv_cpu/test.S new file mode 100644 index 0000000..bc689e5 --- /dev/null +++ b/tb/test_source_code/tb_riscv_cpu/test.S @@ -0,0 +1,9 @@ +# t0 = 0 +li t0, 0 +li t2, 10 +loop_head: +bge t0, t2, loop_end +# Repeated code goes here +addi t0, t0, 1 +j loop_head +loop_end: \ No newline at end of file