From ecfb4a9cc5539cd30a879a99d8d20b9c36dc5eb3 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Tue, 24 Oct 2023 19:39:42 +0900 Subject: [PATCH] Fix: change alu op_code to func --- rtl/alu.v | 4 ++-- rtl/decoder.v | 32 ++++++++++++++++---------------- rtl/risc_v_cpu.v | 2 +- tb/tb_alu.v | 22 +++++++++++----------- 4 files changed, 30 insertions(+), 30 deletions(-) diff --git a/rtl/alu.v b/rtl/alu.v index 8e7ed9d..e472c87 100644 --- a/rtl/alu.v +++ b/rtl/alu.v @@ -1,5 +1,5 @@ module alu (input [31:0] in_a, in_b, - input [3:0] op_code, + input [3:0] func, output reg [31:0] out); `include "alu_func.vh" @@ -10,7 +10,7 @@ module alu (input [31:0] in_a, in_b, always@ (*) begin s_in_a = in_a; s_in_b = in_b; - case (op_code) + case (func) ADD : out <= in_a + in_b; SUB : out <= in_a - in_b; SLL : out <= in_a << in_b; diff --git a/rtl/decoder.v b/rtl/decoder.v index 46b74aa..0f9eeee 100644 --- a/rtl/decoder.v +++ b/rtl/decoder.v @@ -12,9 +12,9 @@ module decoder (input [31:0] instruction, `include "op_code.vh" `include "alu_func.vh" -function [3:0] get_alu_func(input [2:0] op_code, input arithmetic); +function [3:0] get_alu_func(input [2:0] func, input arithmetic); begin - case (op_code) + case (func) 3'b000 : get_alu_func = arithmetic ? SUB : ADD; 3'b001 : get_alu_func = SLL; 3'b010 : get_alu_func = SLT; @@ -28,9 +28,9 @@ function [3:0] get_alu_func(input [2:0] op_code, input arithmetic); end endfunction -function [3:0] get_alu_func_imm(input [2:0] op_code, input arithmetic); +function [3:0] get_alu_func_imm(input [2:0] func, input arithmetic); begin - case (op_code) + case (func) 3'b000 : get_alu_func_imm = ADD; 3'b001 : get_alu_func_imm = SLL; 3'b010 : get_alu_func_imm = SLT; @@ -44,23 +44,23 @@ function [3:0] get_alu_func_imm(input [2:0] op_code, input arithmetic); end endfunction -function [3:0] branch_op_code(input [2:0] op_code); +function [3:0] branch_func(input [2:0] func); begin - case (op_code) - 3'b000 : branch_op_code = 4'b0001; - 3'b001 : branch_op_code = 4'b0001; - 3'b010 : branch_op_code = 4'b0011; - 3'b011 : branch_op_code = 4'b0011; - 3'b100 : branch_op_code = 4'b0011; - 3'b101 : branch_op_code = 4'b0011; - default : branch_op_code = 4'b0000; + case (func) + 3'b000 : branch_func = 4'b0001; + 3'b001 : branch_func = 4'b0001; + 3'b010 : branch_func = 4'b0011; + 3'b011 : branch_func = 4'b0011; + 3'b100 : branch_func = 4'b0011; + 3'b101 : branch_func = 4'b0011; + default : branch_func = 4'b0000; endcase end endfunction -function branch_not(input [2:0] op_code); +function branch_not(input [2:0] func); begin - case (op_code) + case (func) 3'b000 : branch_not = 1; 3'b001 : branch_not = 0; 3'b010 : branch_not = 0; @@ -145,7 +145,7 @@ endfunction reg_sel_out_b = instruction[24:20]; reg_sel_in = 5'b00000; alu_src = 0; - alu_func = branch_op_code(instruction[14:12]); + alu_func = branch_func(instruction[14:12]); mem_we = 0; pc_is_branch = 2'b00; pc_is_jmp = 1; diff --git a/rtl/risc_v_cpu.v b/rtl/risc_v_cpu.v index 2770d01..7b1bdfe 100644 --- a/rtl/risc_v_cpu.v +++ b/rtl/risc_v_cpu.v @@ -59,7 +59,7 @@ module risc_v_cpu (input clock, reset, alu alu ( .in_a(reg_data_out_a), .in_b(alu_in_b), - .op_code(alu_func), + .func(alu_func), .out(alu_out) ); diff --git a/tb/tb_alu.v b/tb/tb_alu.v index 3abc655..f0f0b63 100644 --- a/tb/tb_alu.v +++ b/tb/tb_alu.v @@ -6,19 +6,19 @@ module tb_alu (); reg [31:0] in_a; reg [31:0] in_b; - reg [3:0] op_code; + reg [3:0] func; wire [31:0] out; alu alu ( .in_a(in_a), .in_b(in_b), - .op_code(op_code), + .func(func), .out(out) ); initial begin // ALU - add - op_code = ADD; + func = ADD; in_a = 32'b0; in_b = 32'b0; `assert("alu : 0 + 0", out, 0) @@ -42,7 +42,7 @@ module tb_alu (); `assert("alu : MIN_INT + -1", out, 32'b01111111111111111111111111111111) // ALU - sub - op_code = SUB; + func = SUB; in_a = 32'b0; in_b = 32'b0; `assert("alu : 0 - 0", out, 0) @@ -66,7 +66,7 @@ module tb_alu (); `assert("alu : MIN_INT - -1", out, 32'b10000000000000000000000000000001) // ALU - left shift - op_code = SLL; + func = SLL; in_a = 32'b1; in_b = 32'b1; `assert("alu : 1 << 1", out, 2) @@ -82,7 +82,7 @@ module tb_alu (); `assert("alu : 3 << 31", out, 32'b00000000000000000000000000000000) // ALU - less than - op_code = SLT; + func = SLT; in_a = 32'b0; in_b = 32'b0; `assert("alu : 0 < 0", out, 0) @@ -100,7 +100,7 @@ module tb_alu (); `assert("alu : MIN_INT << MIN_INT + 1", out, 1) // ALU - xor - op_code = XOR; + func = XOR; in_a = 32'b0; in_b = 32'b0; `assert("alu : 0 ^ 0", out, 32'b00000000000000000000000000000000) @@ -120,7 +120,7 @@ module tb_alu (); `assert("alu : 00000011001000010001000011000000 ^ 10101111001011101110111111111011", out, 32'b10101100000011111111111100111011) // ALU - right shift - op_code = SRL; + func = SRL; in_a = 32'b1; in_b = 32'b1; `assert("alu : 1 >> 1", out, 0) @@ -139,7 +139,7 @@ module tb_alu (); `assert("alu : 1000..111 >> 31", out, 32'b00000000000000000000000000000001) // ALU - arithmetic right shift - op_code = SRA; + func = SRA; in_a = 32'b1; in_b = 32'b1; `assert("alu : 1 >>> 1", out, 0) @@ -158,7 +158,7 @@ module tb_alu (); `assert("alu : 1000..111 >>> 31", out, 32'b11111111111111111111111111111111) // ALU - or - op_code = OR; + func = OR; in_a = 32'b0; in_b = 32'b0; `assert("alu : 0 | 0", out, 32'b00000000000000000000000000000000) @@ -178,7 +178,7 @@ module tb_alu (); `assert("alu : 00000011001000010001000011000000 | 10101111001011101110111111111011", out, 32'b10101111001011111111111111111011) // ALU - and - op_code = AND; + func = AND; in_a = 32'b0; in_b = 32'b0; `assert("alu : 0 & 0", out, 32'b00000000000000000000000000000000)