diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v
index c1c8989..a284d65 100644
--- a/tb/tb_risc_v_cpu-dyn.v
+++ b/tb/tb_risc_v_cpu-dyn.v
@@ -8,6 +8,7 @@ module tb_risc_v_cpu ();
     wire [31:0] out;
 
     /* File management variable */
+    integer    file_read_result;
     integer    bin_file_inputs;
     integer    code_file_inputs;
     reg [8:0]  read_instruction_1;
@@ -15,15 +16,12 @@ module tb_risc_v_cpu ();
     reg [8:0]  read_instruction_3;
     reg [8:0]  read_instruction_4;
 
-    reg [113:0]  test [0:256];
-    integer      instruction_addr;
-    reg [5:0]    reg_number;
-    reg [31:0]   reg_test_value;
-    integer curent_addr;
-    integer res;
-    reg [8:0] dump;
-    reg [50*8:1] message;
-    integer size;
+    /* Test data structure */
+    integer     curent_addr;
+    integer     instruction_addr;
+    reg [5:0]   reg_number;
+    reg [31:0]  reg_test_value;
+    reg [113:0] test [0:256];
 
     risc_v_cpu risc_v_cpu (
         .clock(clk),
@@ -86,9 +84,9 @@ module tb_risc_v_cpu ();
         
         while (!$feof(code_file_inputs))
         begin
-            res = $fscanf(code_file_inputs, "%d:%d=%d\n", instruction_addr, reg_number, reg_test_value);
-            if (res != 3) begin     // If fscanf failed, the test file structure is wrong, then exit
-                res = $fgetc(code_file_inputs); // Check if the file is empty
+            file_read_result = $fscanf(code_file_inputs, "%d:%d=%d\n", instruction_addr, reg_number, reg_test_value);
+            if (file_read_result != 3) begin     // If fscanf failed, the test file structure is wrong, then exit
+                file_read_result = $fgetc(code_file_inputs); // Check if the file is empty
                 if (!$feof(code_file_inputs)) begin
                     $display("Parsing test file failed");
                     $finish;
@@ -104,7 +102,7 @@ module tb_risc_v_cpu ();
                     test[instruction_addr][75:44] = reg_test_value;
                 end else if (test[instruction_addr][81:76] == 6'b111111) begin
                     test[instruction_addr][81:76] = reg_number;
-                    test[instruction_addr][113:83] = reg_test_value;
+                    test[instruction_addr][113:82] = reg_test_value;
                 end
             end
         end
@@ -117,32 +115,16 @@ module tb_risc_v_cpu ();
             if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
                 curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
                 `next_cycle
+
+                /* Test State During Execution */
                 if (test[curent_addr][5:0] != 6'b111111) begin
-                    if (test[curent_addr][5:0] < 6'b100000) begin
-                        `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][5:0], test[curent_addr][37:6], risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]])
-                    end else if (test[curent_addr][5:0] == 6'b100000) begin
-                        `assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][37:6], risc_v_cpu.program_counter.pc_addr)
-                    end else if (test[curent_addr][5:0] > 6'b100000) begin
-                        `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][5:0], test[curent_addr][37:6], risc_v_cpu.memory.memory[test[curent_addr][5:0]])
-                    end
+                    `test_result("RUNTIME", curent_addr, 5, 37)
                 end
                 if (test[curent_addr][43:38] != 6'b111111) begin
-                    if (test[curent_addr][43:38] < 6'b100000) begin
-                        `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][43:38], test[curent_addr][75:44], risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]])
-                    end else if (test[curent_addr][43:38] == 6'b100000) begin
-                        `assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][75:44], risc_v_cpu.program_counter.pc_addr)
-                    end else if (test[curent_addr][43:38] > 6'b100000) begin
-                        `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][43:38], test[curent_addr][75:44], risc_v_cpu.memory.memory[test[curent_addr][43:38]])
-                    end
+                    `test_result("RUNTIME", curent_addr, 43, 75)
                 end
                 if (test[curent_addr][81:76] != 6'b111111) begin
-                    if (test[curent_addr][81:76] < 6'b100000) begin
-                        `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][113:83], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]])
-                    end else if (test[curent_addr][81:76] == 6'b100000) begin
-                        `assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][113:83], risc_v_cpu.program_counter.pc_addr)
-                    end else if (test[curent_addr][81:76] > 6'b100000) begin
-                        `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][113:83], risc_v_cpu.memory.memory[test[curent_addr][81:76]])
-                    end
+                    `test_result("RUNTIME", curent_addr, 81, 113)
                 end
             end else begin
                 `next_cycle
@@ -158,14 +140,16 @@ module tb_risc_v_cpu ();
 
         while (!$feof(code_file_inputs))
         begin
-            res = $fscanf(code_file_inputs, "%d=%d\n", reg_number, reg_test_value);
-            if (res != 2) begin     // If fscanf failed, the test file structure is wrong, then exit
-                res = $fgetc(code_file_inputs); // Check if the file is empty
+            file_read_result = $fscanf(code_file_inputs, "%d=%d\n", reg_number, reg_test_value);
+            if (file_read_result != 2) begin     // If fscanf failed, the test file structure is wrong, then exit
+                file_read_result = $fgetc(code_file_inputs); // Check if the file is empty
                 if (!$feof(code_file_inputs)) begin
                     $display("Parsing test file failed");
                     $finish;
                 end
             end else begin
+
+                /* Test State After Execution */
                 if (reg_number < 6'b100000) begin
                     `assert_no_wait_reg("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.registers_bank.registers[reg_number[4:0]])
                 end else if (reg_number == 6'b100000) begin
diff --git a/tb/tb_tools.vh b/tb/tb_tools.vh
index 1a8b416..90f81c0 100644
--- a/tb/tb_tools.vh
+++ b/tb/tb_tools.vh
@@ -29,6 +29,15 @@
     end else \
         $display("\033[0;32m[PASS]\033[0m %s - INSTR: %0d - MEM[%0d] = %0d", message, instr_addr, mem_addr, expected);
 
+`define test_result(message, curent_addr, addr_range, test_range) \
+    if (test[curent_addr][addr_range:addr_range - 5] < 6'b100000) begin \
+        `assert_no_wait_reg(message, curent_addr, test[curent_addr][addr_range:addr_range - 5], test[curent_addr][test_range:test_range - 31], risc_v_cpu.registers_bank.registers[test[curent_addr][addr_range - 1:addr_range - 5]]) \
+    end else if (test[curent_addr][addr_range:addr_range - 5] == 6'b100000) begin \
+        `assert_no_wait_pc(message, curent_addr, test[curent_addr][test_range:test_range - 31], risc_v_cpu.program_counter.pc_addr) \
+    end else if (test[curent_addr][addr_range:addr_range - 5] > 6'b100000) begin \
+        `assert_no_wait_mem(message, curent_addr, test[curent_addr][addr_range:addr_range - 5], test[curent_addr][test_range:test_range - 31], risc_v_cpu.memory.memory[test[curent_addr][addr_range:addr_range - 5]]) \
+    end
+
 `define end_message $display("\033[0;32mIf no \033[0mFAIL\033[0;32m messages, all tests passed!\033[0m");
 
 `define next_cycle \