From c6292d3b4fe9aa2a2863a5ea23534a5903ee52ad Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Sat, 25 Nov 2023 19:34:07 +0900 Subject: [PATCH 1/2] Add: use space more efficiently on test datastructure --- tb/tb_risc_v_cpu-dyn.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index b225657..5aa726d 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -92,6 +92,8 @@ module tb_risc_v_cpu (); $finish; end + instruction_addr = instruction_addr / 4; + if (test[instruction_addr][5:0] == 6'b111111) begin test[instruction_addr][5:0] = reg_number; test[instruction_addr][37:6] = reg_test_value; @@ -111,7 +113,7 @@ module tb_risc_v_cpu (); for (i = 0; i < 100; i = i + 1) begin if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin - curent_addr = risc_v_cpu.program_counter.pc_addr; + curent_addr = risc_v_cpu.program_counter.pc_addr / 4; `next_cycle if (test[curent_addr][5:0] != 6'b111111) begin if (test[curent_addr][5:0] < 6'b100000) begin -- 2.30.2 From ca6d23450d5b6426048eeb2a52883cf7b2a0dcb4 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Sat, 25 Nov 2023 19:38:14 +0900 Subject: [PATCH 2/2] Fix: divide by 4 on entry test too --- tb/tb_risc_v_cpu-dyn.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index 5aa726d..29be8be 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -112,7 +112,7 @@ module tb_risc_v_cpu (); /* Run The Program */ for (i = 0; i < 100; i = i + 1) begin - if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin + if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin curent_addr = risc_v_cpu.program_counter.pc_addr / 4; `next_cycle if (test[curent_addr][5:0] != 6'b111111) begin -- 2.30.2