From 38d35c3a6361ad382013b22f3c009fdded06d9ea Mon Sep 17 00:00:00 2001 From: BOISSON Brice <63735982+BriceBoisson@users.noreply.github.com> Date: Sat, 25 Nov 2023 19:48:46 +0900 Subject: [PATCH 1/2] Update README.md --- README.md | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 19b90be..9e73e16 100644 --- a/README.md +++ b/README.md @@ -10,14 +10,13 @@ This CPU will implement the RV32I ISA, with the following goals: # How to Run the Test -Use the command :\ -```make TARGET=-``` +Use the command : ```make TARGET=-``` -With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_` directory. -```make TARGET=risc_v_cpu-test``` +With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_` directory. \ +Example: `make TARGET=risc_v_cpu-test` -You can remove the dash and `sub_test` argument to run only the non source code based test. -```make TARGET=risc_v_cpu``` +You can remove the dash and `sub_test` argument to run only the non source code based test. \ +Example: `make TARGET=risc_v_cpu` -Or use `all` as a `sub_test` to run all test associated to a `test_bench`. -```make TARGET=risc_v_cpu-all``` +Or use `all` as a `sub_test` to run all test associated to a `test_bench`. \ +Example: `make TARGET=risc_v_cpu-all` -- 2.30.2 From 7949850418bb7dff6493350240dcacfd81e84d53 Mon Sep 17 00:00:00 2001 From: "brice.boisson" Date: Sat, 25 Nov 2023 23:18:24 +0900 Subject: [PATCH 2/2] Add: new test source code + Fix: gen_bin script and bin path --- scripts/gen_test.py | 8 +++--- scripts/get_bin.sh | 8 +++--- tb/tb_risc_v_cpu-dyn.v | 24 ++++++++--------- .../tb_risc_v_cpu/alu_instruction.S | 26 +++++++++++++++++++ 4 files changed, 47 insertions(+), 19 deletions(-) create mode 100644 tb/test_source_code/tb_risc_v_cpu/alu_instruction.S diff --git a/scripts/gen_test.py b/scripts/gen_test.py index 2d0269d..b9eb9f2 100644 --- a/scripts/gen_test.py +++ b/scripts/gen_test.py @@ -12,9 +12,9 @@ test_file = [] def get_test(test, instr_addr, final = False): result = "" - pattern_r = re.compile(r'R\[(\d+)\]=(\d+)') + pattern_r = re.compile(r'R\[(\d+)\]=([+-]?\d+)') pattern_pc = re.compile(r'PC=(\d+)') - pattern_mem = re.compile(r'MEM\[(\d+)\]=(\d+)') + pattern_mem = re.compile(r'MEM\[(\d+)\]=([+-]?\d+)') # Use the patterns to search for matches in the input string match_r = pattern_r.search(test) @@ -40,12 +40,14 @@ def get_test(test, instr_addr, final = False): instr_addr = 0 for line in Lines: - if line.isspace() or ':' in line or line[0] == '#': + if line.isspace() or ':' in line or line[0] == '#' or line[0:2] == '/*' or line[0:2] == '*/' or line[0:2] == ' *': continue elif '#' in line: + print(line) tests = re.split(r'\s|,', line[line.find('#') + 1:]) for test in tests: new_test = get_test(test, instr_addr) + print(new_test) if new_test != "": test_file.append(new_test) instr_addr += 4 diff --git a/scripts/get_bin.sh b/scripts/get_bin.sh index e128fe9..3dce441 100755 --- a/scripts/get_bin.sh +++ b/scripts/get_bin.sh @@ -18,10 +18,10 @@ NAME=$(basename $1) NAME=${NAME%.*} FOLDER=$(dirname $1) -riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o ${NAME}.o -riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf -riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin +riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o test.o +riscv32-unknown-elf-ld -Ttext=0x0 test.o -o test.elf +riscv32-unknown-elf-objcopy -O binary test.elf test.bin -rm -rf ${NAME}.o ${NAME}.elf +rm -rf test.o test.elf exit 0 diff --git a/tb/tb_risc_v_cpu-dyn.v b/tb/tb_risc_v_cpu-dyn.v index 29be8be..58d5873 100644 --- a/tb/tb_risc_v_cpu-dyn.v +++ b/tb/tb_risc_v_cpu-dyn.v @@ -117,29 +117,29 @@ module tb_risc_v_cpu (); `next_cycle if (test[curent_addr][5:0] != 6'b111111) begin if (test[curent_addr][5:0] < 6'b100000) begin - `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]], test[curent_addr][37:6]) + `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][5:0], test[curent_addr][37:6], risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]]) end else if (test[curent_addr][5:0] == 6'b100000) begin - `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][37:6]) + `assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][37:6], risc_v_cpu.program_counter.pc_addr) end else if (test[curent_addr][5:0] > 6'b100000) begin - `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.memory.memory[test[curent_addr][5:0]], test[curent_addr][37:6]) + `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][5:0], test[curent_addr][37:6], risc_v_cpu.memory.memory[test[curent_addr][5:0]]) end end if (test[curent_addr][43:38] != 6'b111111) begin if (test[curent_addr][43:38] < 6'b100000) begin - `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]], test[curent_addr][75:44]) + `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][43:38], test[curent_addr][75:44], risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]]) end else if (test[curent_addr][43:38] == 6'b100000) begin - `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][75:44]) + `assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][75:44], risc_v_cpu.program_counter.pc_addr) end else if (test[curent_addr][43:38] > 6'b100000) begin - `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.memory.memory[test[curent_addr][43:38]], test[curent_addr][75:44]) + `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][43:38], test[curent_addr][75:44], risc_v_cpu.memory.memory[test[curent_addr][43:38]]) end end if (test[curent_addr][81:76] != 6'b111111) begin if (test[curent_addr][81:76] < 6'b100000) begin - `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]], test[curent_addr][81:76]) + `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]]) end else if (test[curent_addr][81:76] == 6'b100000) begin - `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][113:83]) + `assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][113:83], risc_v_cpu.program_counter.pc_addr) end else if (test[curent_addr][81:76] > 6'b100000) begin - `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]], test[curent_addr][81:76]) + `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]]) end end end @@ -163,11 +163,11 @@ module tb_risc_v_cpu (); end if (reg_number < 6'b100000) begin - `assert_no_wait_reg("FINAL", 1'bx, reg_number, risc_v_cpu.registers_bank.registers[reg_number[4:0]], reg_test_value) + `assert_no_wait_reg("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.registers_bank.registers[reg_number[4:0]]) end else if (reg_number == 6'b100000) begin - `assert_no_wait_pc("FINAL", 1'bx, risc_v_cpu.program_counter.pc_addr, reg_test_value) + `assert_no_wait_pc("FINAL", 1'bx, reg_test_value, risc_v_cpu.program_counter.pc_addr) end else if (reg_number > 6'b100000) begin - `assert_no_wait_mem("FINAL", 1'bx, reg_number, risc_v_cpu.memory.memory[test[curent_addr][5:0]], reg_test_value) + `assert_no_wait_mem("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.memory.memory[test[curent_addr][5:0]]) end end diff --git a/tb/test_source_code/tb_risc_v_cpu/alu_instruction.S b/tb/test_source_code/tb_risc_v_cpu/alu_instruction.S new file mode 100644 index 0000000..fa9ede4 --- /dev/null +++ b/tb/test_source_code/tb_risc_v_cpu/alu_instruction.S @@ -0,0 +1,26 @@ +/* + * 0:zero, 1:ra, 2:sp, 3:gp, 4:tp, 5:t0-2, 8:s0/fp + * 9:s1, 10:a0-7, 18:s2-11, 28:t3-6 + */ + +/* addi dest, reg1, imm */ +addi a0, zero, 10 # R[10]=10 +addi a1, zero, 1 # R[11]=1 +/* addi dest, reg1, reg2 */ +add a2, a0, a1 # R[12]=11 +/* sub dest, reg1, reg2 - reg1 - reg2 */ +sub a1, a2, a0 # R[11]=1 +/* add dest, reg1, reg2 - reg1 & reg2 */ +and a2, zero, a1 # R[12]=0 +/* or dest, reg1, reg2 - reg1 | reg2 */ +or a2, a0, a1 # R[12]=11 +/* xor dest, reg1, reg2 - reg1 ^ reg2 */ +xor a0, a2, a1 # R[10]=10 +/* li dest, imm */ +li a0, -10 # R[10]=-10 +/* mv dest, reg1 */ +mv a1, a0 # R[11]=-10 +/* neg dest, reg1 */ +neg a1, a2 # R[11]=-11 + +# R[0]=0 -- 2.30.2