RISC-V_Verilog/tb/tb_tools.vh

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2023-10-23 08:34:37 +00:00
`define assert(message, expected, got) \
#20 \
if(expected !== got) begin \
$display("\033[0;31m[FAILED]\033[0m : %s - got: %d, expected: %d", message, expected, got); \
end
`define end_message $display("\033[0;32mIf no \033[0m[FAILED]\033[0;32m messages, all tests passed!\033[0m");