RISC-V_Verilog

Test add module program counter

#12 by BriceBoisson was merged 2024-01-26 15:13:55 +00:00

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test-add-module_program_counter

Fix: tb reg bank delay first test after end of reset

#11 by BriceBoisson was merged 2023-12-05 04:54:17 +00:00

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test-reg_bank-fix-1

Rework: separate each step of the pipeline in a different component

#10 by BriceBoisson was merged 2023-12-04 02:34:39 +00:00

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multi-cycle

Fix: test 4 mem val to check mem value

#9 by BriceBoisson was merged 2023-12-04 00:43:15 +00:00

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test-fix-mem_test

Fix: fix saved register on stack name

#8 by BriceBoisson was merged 2023-12-03 13:18:09 +00:00

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test-syracuse-2

Add: error message test exec too low

#7 by BriceBoisson was merged 2023-11-30 05:44:49 +00:00

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test-error_message_test_exec_too_low

Add: syracuse test source code

#6 by BriceBoisson was merged 2023-11-30 05:15:31 +00:00

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test-syracuse

Add: new test source code + Fix: gen_bin script and bin path

#5 by BriceBoisson was merged 2023-11-25 14:19:04 +00:00

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test-3

Divide by 4 instruction address to use space more efficiently

#4 by BriceBoisson was merged 2023-11-25 10:39:46 +00:00

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test-2

Add: generate binary for test using gcc

#3 by BriceBoisson was merged 2023-11-20 13:31:13 +00:00

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test

Fix: memory addressing 32 to 8 bits

#2 by BriceBoisson was merged 2023-10-24 12:53:08 +00:00

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risc-v

RISC-V base implementation

#1 by BriceBoisson was merged 2023-10-24 12:20:46 +00:00

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risc-v

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