RISC-V_Verilog/sim/Makefile

all:
	./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test
	vsim -c -do "do simu.do; quit -f"

debug:
	vsim -do "do simu.do"
Add: Makefile 2023-10-11 08:43:36 +00:00			`all:`
Add: test from gcc 2023-11-20 13:20:42 +00:00			`./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test`
Add: Makefile 2023-10-11 08:43:36 +00:00			`vsim -c -do "do simu.do; quit -f"`

			`debug:`
			`vsim -do "do simu.do"`