RISC-V_Verilog/sim/Makefile

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Makefile
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all:
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./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test
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python3 ./../scripts/gen_test.py ../tb/test_source_code/tb_riscv_cpu test.S
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vsim -c -do "do simu.do; quit -f"
debug:
vsim -do "do simu.do"