32 lines
436 B
Coq
32 lines
436 B
Coq
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`timescale 1ns / 1ps
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module tb_risc_v_cpu ();
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// Clock and reset signals
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reg clk;
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reg reset;
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// Design Inputs and outputs
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wire [31:0] out;
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// DUT instantiation
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risc_v_cpu risc_v_cpu (
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.clock(clk),
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.reset(reset),
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.out(out)
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);
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// generate the clock
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initial begin
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clk = 1'b0;
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forever #1 clk = ~clk;
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end
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// Generate the reset
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initial begin
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reset = 1'b1;
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#10
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reset = 1'b0;
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end
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endmodule : tb_risc_v_cpu
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