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RISC-V_Verilog
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Fix: remove work between two test

This commit is contained in:
brice.boisson 2023-11-24 19:42:21 +09:00
parent 9361c493c4
commit 2fa5a5dc60
1 changed files with 1 additions and 1 deletions
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2
scripts/run_test.sh
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@ -1,6 +1,6 @@
#!/bin/sh
rm -rf runtime_test.tmp final_test.tmp
rm -rf work runtime_test.tmp final_test.tmp
SCRIPT_FOLDER="./../scripts"
TEST_BENCH_FOLDER="./../tb"