Fix: reset edge

tb/tb_risc_v_cpu.v

@@ -1,6 +1,8 @@
 `timescale 1ns / 1ps
 
 module tb_risc_v_cpu ();
+integer i;
+
 // Clock and reset signals
 reg clk;
 reg reset;
@@ -15,12 +17,6 @@ risc_v_cpu risc_v_cpu (
     .out(out)
 );
 
-// generate the clock
-initial begin
-    clk = 1'b0;
-    forever #1 clk = ~clk;
-end
-
 // Generate the reset
 initial begin
     reset = 1'b1;
@@ -28,4 +24,13 @@ initial begin
     reset = 1'b0;
 end
 
+
+// generate the clock
+initial begin
+    clk = 1'b0;
+    for (i = 0; i < 100; i = i + 1) begin
+        #1 clk = ~clk;
+    end
+end
+
 endmodule : tb_risc_v_cpu