brice
/
RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add: test PC

This commit is contained in:
brice.boisson 2024-01-26 16:13:21 +01:00
parent 0aae6901e3 d6f7fb498b
commit 36cb472979
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
tb/tb_module_program_counter.v
View File

@ -42,11 +42,14 @@ module tb_module_program_counter ();
#10
reset = 1'b0;
`assert_no_wait("module_program_counter is_jmp: 0, is_branch: 0, alu_not: 0, alu_out: 0, imm: 0", addr, 0)
<<<<<<< HEAD
#2
`assert_no_wait("module_program_counter is_jmp: 0, is_branch: 0, alu_not: 0, alu_out: 0, imm: 0", addr, 4)
#2
`assert_no_wait("module_program_counter is_jmp: 0, is_branch: 0, alu_not: 0, alu_out: 0, imm: 0", addr, 8)
=======
>>>>>>> d6f7fb498b1347201d1c08f9c368aff27a10a77f
`end_message
end