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RISC-V_Verilog
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Update README.md

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BOISSON Brice 2023-11-25 19:48:46 +09:00 committed by GitHub
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@ -10,14 +10,13 @@ This CPU will implement the RV32I ISA, with the following goals:
# How to Run the Test # How to Run the Test
Use the command :\ Use the command : ```make TARGET=<test_bench>-<sub_test>```
```make TARGET=<test_bench>-<sub_test>```
With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_<test_bench>` directory. With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_<test_bench>` directory. \
```make TARGET=risc_v_cpu-test``` Example: `make TARGET=risc_v_cpu-test`
You can remove the dash and `sub_test` argument to run only the non source code based test. You can remove the dash and `sub_test` argument to run only the non source code based test. \
```make TARGET=risc_v_cpu``` Example: `make TARGET=risc_v_cpu`
Or use `all` as a `sub_test` to run all test associated to a `test_bench`. Or use `all` as a `sub_test` to run all test associated to a `test_bench`. \
```make TARGET=risc_v_cpu-all``` Example: `make TARGET=risc_v_cpu-all`