Add: power test source code

rtl/instruction.v

@@ -1,7 +1,7 @@
 module instruction (input  [31:0] address,
                     output [31:0] instruction);
     
-    reg [7:0] memory [1024:0];
+    reg [7:0] memory [1023:0];
 
     assign instruction = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
 

rtl/memory.v

@@ -8,7 +8,7 @@ module memory (input             clock, reset,
 
     `include "mem_func.vh"
     
-    reg [7:0] memory [127:0];
+    reg [7:0] memory [1023:0];
 
     always @(posedge clock, posedge reset) begin
         if (reset == 1)