Add: power test source code

rtl/instruction.v

@@ -1,7 +1,7 @@
 module instruction (input  [31:0] address,
                     output [31:0] instruction);
     
-    reg [7:0] memory [1024:0];
+    reg [7:0] memory [1023:0];
 
     assign instruction = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
 

rtl/memory.v

@@ -8,7 +8,7 @@ module memory (input             clock, reset,
 
     `include "mem_func.vh"
     
-    reg [7:0] memory [127:0];
+    reg [7:0] memory [1023:0];
 
     always @(posedge clock, posedge reset) begin
         if (reset == 1)

tb/tb_risc_v_cpu-dyn.v

@@ -15,7 +15,7 @@ module tb_risc_v_cpu ();
     reg [8:0]  read_instruction_3;
     reg [8:0]  read_instruction_4;
 
-    reg [113:0]  test [0:100];
+    reg [113:0]  test [0:256];
     integer      instruction_addr;
     reg [5:0]    reg_number;
     reg [31:0]   reg_test_value;
@@ -80,7 +80,7 @@ module tb_risc_v_cpu ();
         end
 
         i = 0;
-        for (i = 0; i < 100; i = i + 1) begin   // Fill test data structure of 1,
+        for (i = 0; i < 256; i = i + 1) begin   // Fill test data structure of 1,
             test[i] = {114{1'b1}};              // to represent the empty state
         end
         
@@ -113,7 +113,7 @@ module tb_risc_v_cpu ();
 
         /* Run The Program */
 
-        for (i = 0; i < 300; i = i + 1) begin
+        for (i = 0; i < 10000; i = i + 1) begin
             if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
                 curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
                 `next_cycle

tb/test_source_code/tb_risc_v_cpu/multiplication.S

@@ -7,24 +7,37 @@ li sp, 0
 j test
 
 mult:
-sw a1, 4(sp)
+sw ra, 4(sp)
-sw a2, 8(sp)
+sw a1, 8(sp)
-addi sp, sp, 8
+sw a2, 12(sp)
-li a0, 0
+sw s0, 16(sp)
-li t0, 1
+sw s1, 20(sp)
+sw s2, 24(sp)
+sw s3, 28(sp)
+addi sp, sp, 28
+add s1, a1, zero
+add s2, a2, zero
+li s0, 0
+li s3, 1
 mult_loop_start:
-blt a1, t0, mult_loop_end
+blt s1, s3, mult_loop_end
-and t1, a1, 1
+and t0, s1, 1
-beq t1, zero, mult_even_compute
+beq t0, zero, mult_even_compute
-add a0, a0, a2
+add s0, s0, s2
 mult_even_compute:
-add a2, a2, a2
+add s2, s2, s2
-srl a1, a1, 1
+srl s1, s1, 1
 j mult_loop_start
 mult_loop_end:
-lw a2, 0(sp)
+add a0, s0, zero
-lw a1, -4(sp)
+lw s3, 0(sp)
-addi sp, sp, -8
+lw s2, -4(sp)
+lw s1, -8(sp)
+lw s0, -12(sp)
+lw a2, -16(sp)
+lw a1, -20(sp)
+lw ra, -24(sp)
+addi sp, sp, -28
 jalr ra, ra, 0
 
 test:

tb/test_source_code/tb_risc_v_cpu/power.S

@@ -0,0 +1,132 @@
+/*
+ *  0:zero, 1:ra, 2:sp, 3:gp, 4:tp, 5:t0-2, 8:s0/fp
+ *  9:s1, 10:a0-7, 18:s2-11, 28:t3-6
+ */
+
+li sp, 0
+j test
+
+mult:
+sw ra, 4(sp)
+sw a1, 8(sp)
+sw a2, 12(sp)
+sw s0, 16(sp)
+sw s1, 20(sp)
+sw s2, 24(sp)
+sw s3, 28(sp)
+addi sp, sp, 28
+add s1, a1, zero
+add s2, a2, zero
+li s0, 0
+li s3, 1
+mult_loop_start:
+blt s1, s3, mult_loop_end
+and t0, s1, 1
+beq t0, zero, mult_even_compute
+add s0, s0, s2
+mult_even_compute:
+add s2, s2, s2
+srl s1, s1, 1
+j mult_loop_start
+mult_loop_end:
+add a0, s0, zero
+lw s3, 0(sp)
+lw s2, -4(sp)
+lw s1, -8(sp)
+lw s0, -12(sp)
+lw a2, -16(sp)
+lw a1, -20(sp)
+lw ra, -24(sp)
+addi sp, sp, -28
+jalr ra, ra, 0
+
+power:
+sw ra, 4(sp)
+sw a1, 8(sp)
+sw a2, 12(sp)
+sw s0, 16(sp)
+sw s1, 20(sp)
+sw s2, 24(sp)
+addi sp, sp, 24
+add s1, a1, zero
+add s2, a2, zero
+li s0, 1
+power_loop_start:
+ble s2, zero, power_loop_end
+and t0, s2, 1
+beq t0, zero, power_even_compute
+add a1, s0, zero
+add a2, s1, zero
+jal ra, mult
+add s0, a0, zero
+power_even_compute:
+add a1, s1, zero
+add a2, s1, zero
+jal ra, mult
+add s1, a0, zero
+srl s2, s2, 1
+j power_loop_start
+power_loop_end:
+add a0, s0, zero
+lw s2, 0(sp)
+lw s1, -4(sp)
+lw s0, -8(sp)
+lw a2, -12(sp)
+lw a1, -16(sp)
+lw ra, -20(sp)
+addi sp, sp, -24
+jalr ra, ra, 0
+
+test:
+li a1, 0
+li a2, 0
+jal ra, power
+nop # R[10]=1
+li a1, 0
+li a2, 1
+jal ra, power
+nop # R[10]=0
+li a1, 1
+li a2, 0
+jal ra, power
+nop # R[10]=1
+li a1, 1
+li a2, 1
+jal ra, power
+nop # R[10]=1
+li a1, 2
+li a2, 1
+jal ra, power
+nop # R[10]=2
+li a1, 14
+li a2, 1
+jal ra, power
+nop # R[10]=14
+li a1, 2
+li a2, 2
+jal ra, power
+nop # R[10]=4
+li a1, 3
+li a2, 2
+jal ra, power
+nop # R[10]=9
+li a1, 2
+li a2, 3
+jal ra, power
+nop # R[10]=8
+li a1, 5
+li a2, 2
+jal ra, power
+nop # R[10]=25
+li a1, 4
+li a2, 4
+jal ra, power
+nop # R[10]=256
+li a1, 3
+li a2, 5
+jal ra, power
+nop # R[10]=243
+li a1, 10
+li a2, 4
+jal ra, power
+nop # R[10]=10000