brice/RISC-V_Verilog
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Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench

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brice.boisson
2023-11-28 14:24:30 +09:00
parent 91514de821
commit 5e93084239
4 changed files with 62 additions and 55 deletions
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4
rtl/decoder.v
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@@ -106,7 +106,7 @@ endfunction
alu_src = 1;
alu_func = get_alu_func_imm(instruction[14:12], instruction[30]);
mem_we = 0;
mem_func_in = instruction[13:12];
mem_func_in = 2'b00;
mem_func_out = 3'b000;
pc_is_branch = 2'b00;
pc_is_jmp = 0;
@@ -140,7 +140,7 @@ endfunction
alu_src = 1;
alu_func = 3'b000;
mem_we = 1;
mem_func_in = 2'b00;
mem_func_in = instruction[13:12];
mem_func_out = 3'b000;
pc_is_branch = 2'b00;
pc_is_jmp = 0;

4
rtl/mem_func.vh
View File

@@ -1,8 +1,8 @@
parameter [2:0] LB = 3'b000;
parameter [2:0] LH = 3'b001;
parameter [2:0] LW = 3'b010;
parameter [2:0] LBU = 3'b011;
parameter [2:0] LHU = 3'b100;
parameter [2:0] LBU = 3'b100;
parameter [2:0] LHU = 3'b101;
parameter [2:0] SB = 2'b00;
parameter [2:0] SH = 2'b01;