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Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench

This commit is contained in:
brice.boisson 2023-11-28 14:24:30 +09:00
parent 91514de821
commit 5e93084239
4 changed files with 62 additions and 55 deletions
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4
rtl/decoder.v
View File

@ -106,7 +106,7 @@ endfunction
alu_src = 1; alu_src = 1;
alu_func = get_alu_func_imm(instruction[14:12], instruction[30]); alu_func = get_alu_func_imm(instruction[14:12], instruction[30]);
mem_we = 0; mem_we = 0;
mem_func_in = instruction[13:12]; mem_func_in = 2'b00;
mem_func_out = 3'b000; mem_func_out = 3'b000;
pc_is_branch = 2'b00; pc_is_branch = 2'b00;
pc_is_jmp = 0; pc_is_jmp = 0;
@ -140,7 +140,7 @@ endfunction
alu_src = 1; alu_src = 1;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 1; mem_we = 1;
mem_func_in = 2'b00; mem_func_in = instruction[13:12];
mem_func_out = 3'b000; mem_func_out = 3'b000;
pc_is_branch = 2'b00; pc_is_branch = 2'b00;
pc_is_jmp = 0; pc_is_jmp = 0;

4
rtl/mem_func.vh
View File

@ -1,8 +1,8 @@
parameter [2:0] LB = 3'b000; parameter [2:0] LB = 3'b000;
parameter [2:0] LH = 3'b001; parameter [2:0] LH = 3'b001;
parameter [2:0] LW = 3'b010; parameter [2:0] LW = 3'b010;
parameter [2:0] LBU = 3'b011; parameter [2:0] LBU = 3'b100;
parameter [2:0] LHU = 3'b100; parameter [2:0] LHU = 3'b101;
parameter [2:0] SB = 2'b00; parameter [2:0] SB = 2'b00;
parameter [2:0] SH = 2'b01; parameter [2:0] SH = 2'b01;

6
tb/tb_risc_v_cpu-dyn.v
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@ -113,7 +113,7 @@ module tb_risc_v_cpu ();
/* Run The Program */ /* Run The Program */
for (i = 0; i < 200; i = i + 1) begin for (i = 0; i < 300; i = i + 1) begin
if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
curent_addr = risc_v_cpu.program_counter.pc_addr / 4; curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
`next_cycle `next_cycle
@ -137,11 +137,11 @@ module tb_risc_v_cpu ();
end end
if (test[curent_addr][81:76] != 6'b111111) begin if (test[curent_addr][81:76] != 6'b111111) begin
if (test[curent_addr][81:76] < 6'b100000) begin if (test[curent_addr][81:76] < 6'b100000) begin
`assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]]) `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][113:83], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]])
end else if (test[curent_addr][81:76] == 6'b100000) begin end else if (test[curent_addr][81:76] == 6'b100000) begin
`assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][113:83], risc_v_cpu.program_counter.pc_addr) `assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][113:83], risc_v_cpu.program_counter.pc_addr)
end else if (test[curent_addr][81:76] > 6'b100000) begin end else if (test[curent_addr][81:76] > 6'b100000) begin
`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]]) `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][113:83], risc_v_cpu.memory.memory[test[curent_addr][81:76]])
end end
end end
end else begin end else begin

103
tb/test_source_code/tb_risc_v_cpu/multiplication.S
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@ -3,61 +3,68 @@
* 9:s1, 10:a0-7, 18:s2-11, 28:t3-6 * 9:s1, 10:a0-7, 18:s2-11, 28:t3-6
*/ */
li sp, 0
j test j test
mult: mult:
sw a1, 4(sp)
sw a2, 8(sp)
addi sp, sp, 8
li a0, 0 li a0, 0
li a2, 1 li t0, 1
mult_loop_start: mult_loop_start:
blt t1, a2, mult_loop_end blt a1, t0, mult_loop_end
and a1, t1, 1 and t1, a1, 1
beq a1, zero, mult_even_compute beq t1, zero, mult_even_compute
add a0, a0, t2 add a0, a0, a2
mult_even_compute: mult_even_compute:
add t2, t2, t2 add a2, a2, a2
srl t1, t1, 1 srl a1, a1, 1
j mult_loop_start j mult_loop_start
mult_loop_end: mult_loop_end:
jalr ra, t0, 0 lw a2, 0(sp)
lw a1, -4(sp)
addi sp, sp, -8
jalr ra, ra, 0
test: test:
li t1, 0 li a1, 0
li t2, 0 li a2, 0
jal t0, mult jal ra, mult
nop # R[10]=0 nop # R[10]=0, R[11]=0, R[12]=0
li t1, 0 li a1, 0
li t2, 1 li a2, 1
jal t0, mult jal ra, mult
nop # R[10]=0 nop # R[10]=0, R[11]=0, R[12]=1
li t1, 1 li a1, 1
li t2, 0 li a2, 0
jal t0, mult jal ra, mult
nop # R[10]=0 nop # R[10]=0, R[11]=1, R[12]=0
li t1, 1 li a1, 1
li t2, 1 li a2, 1
jal t0, mult jal ra, mult
nop # R[10]=1 nop # R[10]=1, R[11]=1, R[12]=1
li t1, 2 li a1, 2
li t2, 1 li a2, 1
jal t0, mult jal ra, mult
nop # R[10]=2 nop # R[10]=2, R[11]=2, R[12]=1
li t1, 1 li a1, 1
li t2, 3 li a2, 3
jal t0, mult jal ra, mult
nop # R[10]=3 nop # R[10]=3, R[11]=1, R[12]=3
li t1, 2 li a1, 2
li t2, 2 li a2, 2
jal t0, mult jal ra, mult
nop # R[10]=4 nop # R[10]=4, R[11]=2, R[12]=2
li t1, 2 li a1, 2
li t2, 3 li a2, 3
jal t0, mult jal ra, mult
nop # R[10]=6 nop # R[10]=6, R[11]=2, R[12]=3
li t1, 5 li a1, 5
li t2, 3 li a2, 3
jal t0, mult jal ra, mult
nop # R[10]=15 nop # R[10]=15, R[11]=5, R[12]=3
li t1, 5 li a1, 5
li t2, 25 li a2, 25
jal t0, mult jal ra, mult
nop # R[10]=125 nop # R[10]=125, R[11]=5, R[12]=25