Fix: memory addressing 32 to 8 bits

rtl/instruction.v

@@ -1,8 +1,8 @@
 module instruction (input  [31:0] address,
                     output [31:0] instruction);
     
-    reg [31:0] memory [63:0];
+    reg [7:0] memory [63:0];
 
-    assign instruction = memory[address];
+    assign instruction = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
 
 endmodule

rtl/memory.v

@@ -4,15 +4,18 @@ module memory (input         clock, reset,
                input  [31:0] data_in,
                output [31:0] data_out);
     
-    reg [63:0] memory [31:0];
+    reg [7:0] memory [63:0];
 
     always @(posedge clock, posedge reset) begin
         if (reset == 1)
-            memory[0] <= 32'b0;
+            memory[0] <= 8'b0;
         else if (we == 1)
-            memory[address] <= data_in;
+            memory[address]     <= data_in[7:0];
+            memory[address + 1] <= data_in[15:8];
+            memory[address + 2] <= data_in[23:16];
+            memory[address + 3] <= data_in[31:24];
     end
 
-    assign data_out = memory[address];
+    assign data_out = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
 
 endmodule