brice/RISC-V_Verilog
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Add: new make way enabling multiple asm generated test

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brice.boisson
2023-11-22 11:35:08 +09:00
parent e2ca11548c
commit 6f4f7f6969
8 changed files with 102 additions and 31 deletions
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6
tb/tb_risc_v_cpu-dyn.v
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@@ -40,7 +40,7 @@ module tb_risc_v_cpu ();
/* Loading Test From File */
/* Loading Binary File */
bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r");
bin_file_inputs = $fopen("./test.bin", "r");
if (bin_file_inputs == 0) begin
$display("bin file handle was NULL");
$finish;
@@ -71,7 +71,7 @@ module tb_risc_v_cpu ();
$fclose(bin_file_inputs);
/* Extract Value to Test From File */
code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.tmp", "r");
code_file_inputs = $fopen("./runtime_test.tmp", "r");
if (code_file_inputs == 0) begin
$display("source code file handle was NULL");
$finish;
@@ -144,7 +144,7 @@ module tb_risc_v_cpu ();
end
/* Test State After Execution */
code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.final.tmp", "r");
code_file_inputs = $fopen("./final_test.tmp", "r");
if (code_file_inputs == 0) begin
$display("source code file handle was NULL");
$finish;

10
tb/test_source_code/tb_risc_v_cpu/test.S Normal file
View File

@@ -0,0 +1,10 @@
# t0 = 0
li t0, 0 # R[5]=0
li t2, 10 # R[7]=10
loop_head:
bge t0, t2, loop_end
# Repeated code goes here
addi t0, t0, 1 # PC=16
j loop_head
loop_end:
# R[0]=0