Add: new make way enabling multiple asm generated test
This commit is contained in:
parent
e2ca11548c
commit
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15
Makefile
15
Makefile
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@ -1,12 +1,9 @@
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all: simulation
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all:
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$(MAKE) -C sim $@
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$(MAKE) -C sim $@
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debug: simulation
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debug:
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$(MAKE) -C sim $@
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$(MAKE) -C sim $@
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simulation:
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./scripts/gen_simu_do.sh $(TARGET) $(WAVE)
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clean:
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clean:
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rm -rf sim/work
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rm -rf sim/work
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rm -rf work
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rm -rf work
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@ -14,7 +11,7 @@ clean:
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rm -rf transcript
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rm -rf transcript
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rm -rf sim/vsim.wlf
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rm -rf sim/vsim.wlf
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rm -rf sim/simu.do
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rm -rf sim/simu.do
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rm -rf tb/test_source_code/**/*.bin
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rm -rf sim/*.bin
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rm -rf tb/test_source_code/**/*.elf
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rm -rf sim/*.elf
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rm -rf tb/test_source_code/**/*.o
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rm -rf sim/*.o
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rm -rf tb/test_source_code/**/*.tmp
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rm -rf sim/*.tmp
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@ -9,14 +9,14 @@ TB_FILE_NAME=tb_$1
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FILE_NAME=$(echo "$1" | sed 's/\([[:alnum:]_]*\)[-.].*/\1/')
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FILE_NAME=$(echo "$1" | sed 's/\([[:alnum:]_]*\)[-.].*/\1/')
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echo 'puts "Simulation script for ModelSim"
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echo 'puts "Simulation script for ModelSim"
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' > ./sim/simu.do
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' > ./simu.do
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# test if "$1".v and tb_"$1".v files exist
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# test if "$1".v and tb_"$1".v files exist
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if [ ! -f "rtl/""$FILE_NAME"".v" ]; then
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if [ ! -f "../rtl/""$FILE_NAME"".v" ]; then
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echo "Error: $FILE_NAME.v file not found!"
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echo "Error: $FILE_NAME.v file not found!"
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exit 1
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exit 1
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fi
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fi
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if [ ! -f "tb/""$TB_FILE_NAME"".v" ]; then
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if [ ! -f "../tb/""$TB_FILE_NAME"".v" ]; then
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echo "Error: ""$TB_FILE_NAME"".v file not found!"
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echo "Error: ""$TB_FILE_NAME"".v file not found!"
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exit 1
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exit 1
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fi
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fi
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@ -24,13 +24,13 @@ fi
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echo 'vlib work
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echo 'vlib work
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vlog ../rtl/*.v
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vlog ../rtl/*.v
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vlog ../tb/'"$TB_FILE_NAME"'.v
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vlog ../tb/'"$TB_FILE_NAME"'.v
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' >> ./sim/simu.do
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' >> ./simu.do
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echo 'vsim tb_'"$FILE_NAME"'
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echo 'vsim tb_'"$FILE_NAME"'
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' >> ./sim/simu.do
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' >> ./simu.do
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# loop through all arguments from $3
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# loop through all arguments from $3
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echo 'run -all' >> ./sim/simu.do
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echo 'run -all' >> ./simu.do
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exit 0
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exit 0
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@ -1,11 +1,11 @@
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import re
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import re
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import sys
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import sys
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if len(sys.argv) != 3:
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if len(sys.argv) != 2:
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print("Usage: python3 gen_test.py <path> <filename>")
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print("Usage: python3 gen_test.py <filename>")
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exit(1)
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exit(1)
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source_code = open(sys.argv[1] + "/" + sys.argv[2], 'r')
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source_code = open(sys.argv[1], 'r')
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Lines = source_code.readlines()
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Lines = source_code.readlines()
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test_file = []
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test_file = []
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@ -52,7 +52,7 @@ for line in Lines:
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# save test_file to a file named test.tmp
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# save test_file to a file named test.tmp
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with open(sys.argv[1] + '/test.tmp', 'w') as f:
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with open('runtime_test.tmp', 'w') as f:
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for item in test_file:
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for item in test_file:
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f.write("%s\n" % item)
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f.write("%s\n" % item)
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@ -71,6 +71,6 @@ for line in reversed(Lines):
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break
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break
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# save test_file to a file named test.tmp
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# save test_file to a file named test.tmp
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with open(sys.argv[1] + '/test.final.tmp', 'w') as f:
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with open('final_test.tmp', 'w') as f:
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for item in final_test_file:
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for item in final_test_file:
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f.write("%s\n" % item)
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f.write("%s\n" % item)
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@ -1,4 +1,4 @@
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#!/bin/bash
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#!/bin/sh
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if [ ! command -v riscv32-unknown-elf-as &> /dev/null ] \
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if [ ! command -v riscv32-unknown-elf-as &> /dev/null ] \
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|| [ ! command -v riscv32-unknown-elf-ld &> /dev/null ] \
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|| [ ! command -v riscv32-unknown-elf-ld &> /dev/null ] \
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@ -14,10 +14,14 @@ then
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exit 1
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exit 1
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fi
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fi
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NAME=$1
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NAME=$(basename $1)
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NAME=${NAME%.*}
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FOLDER=$(dirname $1)
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riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${NAME}.S -o ${NAME}.o
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riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o ${NAME}.o
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riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf
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riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf
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riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin
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riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin
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# rm -rf ${NAME}.o ${NAME}.elf
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rm -rf ${NAME}.o ${NAME}.elf
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exit 0
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@ -0,0 +1,62 @@
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#!/bin/sh
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rm -rf runtime_test.tmp final_test.tmp
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SCRIPT_FOLDER="./../scripts"
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TEST_BENCH_FOLDER="./../tb"
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TEST_BENCH="${1%-*}"
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TEST_FOLDER="test_source_code/tb_""$TEST_BENCH"
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TEST_FILE=$(echo "${1}" | awk -F'-' '{if (NF>1) {print $NF}}')
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TEST_BENCH_PATH="$TEST_BENCH_FOLDER""/tb_""$TEST_BENCH"
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if [ ! -f "$TEST_BENCH_PATH"".v" ]; then
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echo "testbench: ""$TEST_BENCH_PATH"": does not exit"
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exit 1
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fi
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run_test ()
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{
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TEST_FILE_PATH=$1
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if [ ! -f $TEST_FILE_PATH ]; then
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echo "test file: ""$TEST_FILE_PATH"": does not exit"
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exit 1
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fi
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./${SCRIPT_FOLDER}/get_bin.sh $TEST_FILE_PATH
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python3 ./${SCRIPT_FOLDER}/gen_test.py $TEST_FILE_PATH
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if [ -z $2 ]; then
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vsim -c -do "do simu.do; quit -f"
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else
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vsim -do "do simu.do"
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fi
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}
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if [ -z "$TEST_FILE" ] || [ "$TEST_FILE" = "all" ]; then
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./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH"
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if [ -z $2 ]; then
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vsim -c -do "do simu.do; quit -f"
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else
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vsim -do "do simu.do"
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fi
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fi
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if [ ! -z "$TEST_FILE" ]; then
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TEST_BENCH_PATH="$TEST_BENCH_FOLDER""/tb_""$TEST_BENCH""-dyn"
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if [ ! -f "$TEST_BENCH_PATH"".v" ]; then
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exit 0
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fi
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./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH""-dyn"
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if [ "$TEST_FILE" == "all" ]; then
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for f in "$TEST_BENCH_FOLDER""/""$TEST_FOLDER""/*"; do
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run_test $f $2
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done
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else
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run_test $TEST_FILE".S" $2
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fi
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fi
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exit 0
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@ -1,7 +1,5 @@
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all:
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all:
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./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test
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./../scripts/run_test.sh $(TARGET)
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python3 ./../scripts/gen_test.py ../tb/test_source_code/tb_riscv_cpu test.S
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vsim -c -do "do simu.do; quit -f"
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debug:
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debug:
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vsim -do "do simu.do"
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./../scripts/run_test.sh $(TARGET) debug
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@ -40,7 +40,7 @@ module tb_risc_v_cpu ();
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/* Loading Test From File */
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/* Loading Test From File */
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/* Loading Binary File */
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/* Loading Binary File */
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bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r");
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bin_file_inputs = $fopen("./test.bin", "r");
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if (bin_file_inputs == 0) begin
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if (bin_file_inputs == 0) begin
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$display("bin file handle was NULL");
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$display("bin file handle was NULL");
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$finish;
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$finish;
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@ -71,7 +71,7 @@ module tb_risc_v_cpu ();
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$fclose(bin_file_inputs);
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$fclose(bin_file_inputs);
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/* Extract Value to Test From File */
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/* Extract Value to Test From File */
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code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.tmp", "r");
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code_file_inputs = $fopen("./runtime_test.tmp", "r");
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if (code_file_inputs == 0) begin
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if (code_file_inputs == 0) begin
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$display("source code file handle was NULL");
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$display("source code file handle was NULL");
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$finish;
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$finish;
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@ -144,7 +144,7 @@ module tb_risc_v_cpu ();
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end
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end
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/* Test State After Execution */
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/* Test State After Execution */
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code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.final.tmp", "r");
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code_file_inputs = $fopen("./final_test.tmp", "r");
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if (code_file_inputs == 0) begin
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if (code_file_inputs == 0) begin
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$display("source code file handle was NULL");
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$display("source code file handle was NULL");
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$finish;
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$finish;
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@ -0,0 +1,10 @@
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# t0 = 0
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li t0, 0 # R[5]=0
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li t2, 10 # R[7]=10
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loop_head:
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bge t0, t2, loop_end
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# Repeated code goes here
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addi t0, t0, 1 # PC=16
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j loop_head
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loop_end:
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# R[0]=0
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