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Add: new make way enabling multiple asm generated test

This commit is contained in:
brice.boisson 2023-11-22 11:35:08 +09:00
parent e2ca11548c
commit 6f4f7f6969
8 changed files with 102 additions and 31 deletions
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15
Makefile
View File

@ -1,12 +1,9 @@
all: simulation
all:
$(MAKE) -C sim $@
debug: simulation
debug:
$(MAKE) -C sim $@
simulation:
./scripts/gen_simu_do.sh $(TARGET) $(WAVE)
clean:
rm -rf sim/work
rm -rf work
@ -14,7 +11,7 @@ clean:
rm -rf transcript
rm -rf sim/vsim.wlf
rm -rf sim/simu.do
rm -rf tb/test_source_code/**/*.bin
rm -rf tb/test_source_code/**/*.elf
rm -rf tb/test_source_code/**/*.o
rm -rf tb/test_source_code/**/*.tmp
rm -rf sim/*.bin
rm -rf sim/*.elf
rm -rf sim/*.o
rm -rf sim/*.tmp

12
scripts/gen_simu_do.sh
View File

@ -9,14 +9,14 @@ TB_FILE_NAME=tb_$1
FILE_NAME=$(echo "$1" | sed 's/\([[:alnum:]_]*\)[-.].*/\1/')
echo 'puts "Simulation script for ModelSim"
' > ./sim/simu.do
' > ./simu.do
# test if "$1".v and tb_"$1".v files exist
if [ ! -f "rtl/""$FILE_NAME"".v" ]; then
if [ ! -f "../rtl/""$FILE_NAME"".v" ]; then
echo "Error: $FILE_NAME.v file not found!"
exit 1
fi
if [ ! -f "tb/""$TB_FILE_NAME"".v" ]; then
if [ ! -f "../tb/""$TB_FILE_NAME"".v" ]; then
echo "Error: ""$TB_FILE_NAME"".v file not found!"
exit 1
fi
@ -24,13 +24,13 @@ fi
echo 'vlib work
vlog ../rtl/*.v
vlog ../tb/'"$TB_FILE_NAME"'.v
' >> ./sim/simu.do
' >> ./simu.do
echo 'vsim tb_'"$FILE_NAME"'
' >> ./sim/simu.do
' >> ./simu.do
# loop through all arguments from $3
echo 'run -all' >> ./sim/simu.do
echo 'run -all' >> ./simu.do
exit 0

10
scripts/gen_test.py
View File

@ -1,11 +1,11 @@
import re
import sys
if len(sys.argv) != 3:
print("Usage: python3 gen_test.py <path> <filename>")
if len(sys.argv) != 2:
print("Usage: python3 gen_test.py <filename>")
exit(1)
source_code = open(sys.argv[1] + "/" + sys.argv[2], 'r')
source_code = open(sys.argv[1], 'r')
Lines = source_code.readlines()
test_file = []
@ -52,7 +52,7 @@ for line in Lines:
# save test_file to a file named test.tmp
with open(sys.argv[1] + '/test.tmp', 'w') as f:
with open('runtime_test.tmp', 'w') as f:
for item in test_file:
f.write("%s\n" % item)
@ -71,6 +71,6 @@ for line in reversed(Lines):
break
# save test_file to a file named test.tmp
with open(sys.argv[1] + '/test.final.tmp', 'w') as f:
with open('final_test.tmp', 'w') as f:
for item in final_test_file:
f.write("%s\n" % item)

12
scripts/get_bin.sh
View File

@ -1,4 +1,4 @@
#!/bin/bash
#!/bin/sh
if [ ! command -v riscv32-unknown-elf-as &> /dev/null ] \
|| [ ! command -v riscv32-unknown-elf-ld &> /dev/null ] \
@ -14,10 +14,14 @@ then
exit 1
fi
NAME=$1
NAME=$(basename $1)
NAME=${NAME%.*}
FOLDER=$(dirname $1)
riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${NAME}.S -o ${NAME}.o
riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o ${NAME}.o
riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf
riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin
# rm -rf ${NAME}.o ${NAME}.elf
rm -rf ${NAME}.o ${NAME}.elf
exit 0

62
scripts/run_test.sh Executable file
View File

@ -0,0 +1,62 @@
#!/bin/sh
rm -rf runtime_test.tmp final_test.tmp
SCRIPT_FOLDER="./../scripts"
TEST_BENCH_FOLDER="./../tb"
TEST_BENCH="${1%-*}"
TEST_FOLDER="test_source_code/tb_""$TEST_BENCH"
TEST_FILE=$(echo "${1}" | awk -F'-' '{if (NF>1) {print $NF}}')
TEST_BENCH_PATH="$TEST_BENCH_FOLDER""/tb_""$TEST_BENCH"
if [ ! -f "$TEST_BENCH_PATH"".v" ]; then
echo "testbench: ""$TEST_BENCH_PATH"": does not exit"
exit 1
fi
run_test ()
{
TEST_FILE_PATH=$1
if [ ! -f $TEST_FILE_PATH ]; then
echo "test file: ""$TEST_FILE_PATH"": does not exit"
exit 1
fi
./${SCRIPT_FOLDER}/get_bin.sh $TEST_FILE_PATH
python3 ./${SCRIPT_FOLDER}/gen_test.py $TEST_FILE_PATH
if [ -z $2 ]; then
vsim -c -do "do simu.do; quit -f"
else
vsim -do "do simu.do"
fi
}
if [ -z "$TEST_FILE" ] || [ "$TEST_FILE" = "all" ]; then
./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH"
if [ -z $2 ]; then
vsim -c -do "do simu.do; quit -f"
else
vsim -do "do simu.do"
fi
fi
if [ ! -z "$TEST_FILE" ]; then
TEST_BENCH_PATH="$TEST_BENCH_FOLDER""/tb_""$TEST_BENCH""-dyn"
if [ ! -f "$TEST_BENCH_PATH"".v" ]; then
exit 0
fi
./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH""-dyn"
if [ "$TEST_FILE" == "all" ]; then
for f in "$TEST_BENCH_FOLDER""/""$TEST_FOLDER""/*"; do
run_test $f $2
done
else
run_test $TEST_FILE".S" $2
fi
fi
exit 0

6
sim/Makefile
View File

@ -1,7 +1,5 @@
all:
./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test
python3 ./../scripts/gen_test.py ../tb/test_source_code/tb_riscv_cpu test.S
vsim -c -do "do simu.do; quit -f"
./../scripts/run_test.sh $(TARGET)
debug:
vsim -do "do simu.do"
./../scripts/run_test.sh $(TARGET) debug

6
tb/tb_risc_v_cpu-dyn.v
View File

@ -40,7 +40,7 @@ module tb_risc_v_cpu ();
/* Loading Test From File */
/* Loading Binary File */
bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r");
bin_file_inputs = $fopen("./test.bin", "r");
if (bin_file_inputs == 0) begin
$display("bin file handle was NULL");
$finish;
@ -71,7 +71,7 @@ module tb_risc_v_cpu ();
$fclose(bin_file_inputs);
/* Extract Value to Test From File */
code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.tmp", "r");
code_file_inputs = $fopen("./runtime_test.tmp", "r");
if (code_file_inputs == 0) begin
$display("source code file handle was NULL");
$finish;
@ -144,7 +144,7 @@ module tb_risc_v_cpu ();
end
/* Test State After Execution */
code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.final.tmp", "r");
code_file_inputs = $fopen("./final_test.tmp", "r");
if (code_file_inputs == 0) begin
$display("source code file handle was NULL");
$finish;

10
tb/test_source_code/tb_risc_v_cpu/test.S Normal file
View File

@ -0,0 +1,10 @@
# t0 = 0
li t0, 0 # R[5]=0
li t2, 10 # R[7]=10
loop_head:
bge t0, t2, loop_end
# Repeated code goes here
addi t0, t0, 1 # PC=16
j loop_head
loop_end:
# R[0]=0