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Fix: clean name [3]

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brice.boisson
2023-10-23 14:15:21 +09:00
parent 2c9abe91af
commit 72d688018b
11 changed files with 140 additions and 191 deletions
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61
tb/tb_alu.v
View File

@@ -1,41 +1,36 @@
`timescale 1ns / 1ps
module tb_alu ();
// Design Inputs and outputs
reg [31:0] in_a;
reg [31:0] in_b;
reg [2:0] op_code;
wire [31:0] out;
reg [31:0] in_a;
reg [31:0] in_b;
reg [2:0] op_code;
wire [31:0] out;
// DUT instantiation
alu alu (
.input_a(in_a),
.input_b(in_b),
.op_code(op_code),
.out(out)
);
alu alu (
.in_a(in_a),
.in_b(in_b),
.op_code(op_code),
.out(out)
);
// Test stimulus
initial begin
// Use the monitor task to display the FPGA IO
$monitor("time=%3d, in_a=%d, in_b=%d, ctrl=%b, q=%d \n",
$time, in_a, in_b, op_code, out);
initial begin
$monitor("time=%3d, in_a=%d, in_b=%d, ctrl=%b, q=%d \n",
$time, in_a, in_b, op_code, out);
// Generate each input with a 20 ns delay between them
in_a = 1'b0;
in_b = 1'b0;
op_code = 3'b000;
#20
if (out !== 0) $display("[FAILED] output should be 0");
in_a = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
in_b = 1'b1;
#20
if (out !== 2) $display("[FAILED] output should be 2");
op_code = 3'b001;
#20
if (out !== 2) $display("[FAILED] output should be 2");
end
in_a = 1'b0;
in_b = 1'b0;
op_code = 3'b000;
#20
if (out !== 0) $display("[FAILED] output should be 0");
in_a = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
in_b = 1'b1;
#20
if (out !== 2) $display("[FAILED] output should be 2");
op_code = 3'b001;
#20
if (out !== 2) $display("[FAILED] output should be 2");
end
endmodule : tb_alu

84
tb/tb_mux2_1.v
View File

@@ -1,61 +1,39 @@
`timescale 1ns / 1ps
module tb_mux2_1 ();
// Clock and reset signals
reg clk;
reg reset;
reg ctrl;
reg [31:0] in_a;
reg [31:0] in_b;
wire [31:0] out;
// Design Inputs and outputs
reg [31:0] in_a;
reg [31:0] in_b;
reg ctrl;
wire [31:0] out;
mux2_1 mux (
.S(ctrl),
.A(in_a),
.B(in_b),
.O(out)
);
// DUT instantiation
mux2_1 mux (
.S(ctrl),
.A(in_a),
.B(in_b),
.O(out)
);
initial begin
$monitor("time=%3d, in_a=%d, in_b=%d, ctrl=%b, q=%d \n",
$time, in_a, in_b, ctrl, out);
// generate the clock
initial begin
clk = 1'b0;
// forever #1 clk = ~clk;
end
// Generate the reset
initial begin
reset = 1'b1;
#10
reset = 1'b0;
end
// Test stimulus
initial begin
// Use the monitor task to display the FPGA IO
$monitor("time=%3d, in_a=%d, in_b=%d, ctrl=%b, q=%d \n",
$time, in_a, in_b, ctrl, out);
// Generate each input with a 20 ns delay between them
in_a = 1'b0;
in_b = 1'b0;
ctrl = 1'b0;
#20
if (out !== 0) $display("[FAILED] output should be 0");
in_a = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
ctrl = 1'b1;
in_a = 1'b0;
in_b = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
ctrl = 1'b0;
in_a = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
end
in_a = 1'b0;
in_b = 1'b0;
ctrl = 1'b0;
#20
if (out !== 0) $display("[FAILED] output should be 0");
in_a = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
ctrl = 1'b1;
in_a = 1'b0;
in_b = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
ctrl = 1'b0;
in_a = 1'b1;
#20
if (out !== 1) $display("[FAILED] output should be 1");
end
endmodule : tb_mux2_1

48
tb/tb_risc_v_cpu.v
View File

@@ -1,36 +1,28 @@
`timescale 1ns / 1ps
module tb_risc_v_cpu ();
integer i;
reg clk;
reg reset;
integer i;
wire [31:0] out;
// Clock and reset signals
reg clk;
reg reset;
risc_v_cpu risc_v_cpu (
.clock(clk),
.reset(reset),
.out(out)
);
// Design Inputs and outputs
wire [31:0] out;
// DUT instantiation
risc_v_cpu risc_v_cpu (
.clock(clk),
.reset(reset),
.out(out)
);
// Generate the reset
initial begin
reset = 1'b1;
#10
reset = 1'b0;
end
// generate the clock
initial begin
clk = 1'b0;
for (i = 0; i < 100; i = i + 1) begin
#1 clk = ~clk;
initial begin
reset = 1'b1;
#10
reset = 1'b0;
end
initial begin
clk = 1'b0;
for (i = 0; i < 100; i = i + 1) begin
#1 clk = ~clk;
end
end
end
endmodule : tb_risc_v_cpu