brice/RISC-V_Verilog
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Add: new test source code + Fix: gen_bin script and bin path

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brice.boisson
2023-11-25 23:18:24 +09:00
parent 0a032b36b0
commit 7949850418
4 changed files with 47 additions and 19 deletions
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8
scripts/gen_test.py
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@@ -12,9 +12,9 @@ test_file = []
def get_test(test, instr_addr, final = False):
result = ""
pattern_r = re.compile(r'R\[(\d+)\]=(\d+)')
pattern_r = re.compile(r'R\[(\d+)\]=([+-]?\d+)')
pattern_pc = re.compile(r'PC=(\d+)')
pattern_mem = re.compile(r'MEM\[(\d+)\]=(\d+)')
pattern_mem = re.compile(r'MEM\[(\d+)\]=([+-]?\d+)')
# Use the patterns to search for matches in the input string
match_r = pattern_r.search(test)
@@ -40,12 +40,14 @@ def get_test(test, instr_addr, final = False):
instr_addr = 0
for line in Lines:
if line.isspace() or ':' in line or line[0] == '#':
if line.isspace() or ':' in line or line[0] == '#' or line[0:2] == '/*' or line[0:2] == '*/' or line[0:2] == ' *':
continue
elif '#' in line:
print(line)
tests = re.split(r'\s|,', line[line.find('#') + 1:])
for test in tests:
new_test = get_test(test, instr_addr)
print(new_test)
if new_test != "":
test_file.append(new_test)
instr_addr += 4

8
scripts/get_bin.sh
View File

@@ -18,10 +18,10 @@ NAME=$(basename $1)
NAME=${NAME%.*}
FOLDER=$(dirname $1)
riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o ${NAME}.o
riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf
riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin
riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o test.o
riscv32-unknown-elf-ld -Ttext=0x0 test.o -o test.elf
riscv32-unknown-elf-objcopy -O binary test.elf test.bin
rm -rf ${NAME}.o ${NAME}.elf
rm -rf test.o test.elf
exit 0