brice/RISC-V_Verilog
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Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)

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This commit is contained in:
brice.boisson
2023-10-27 12:46:13 +09:00
parent ae0d20b5e7
commit 89a66cd244
7 changed files with 174 additions and 109 deletions
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22
rtl/module_alu.v Normal file
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@@ -0,0 +1,22 @@
module module_alu (input src,
input [3:0] func,
input [31:0] reg_in_a, reg_in_b, imm,
output [31:0] out);
wire [31:0] in_b;
mux2_1 mux2_in_b (
.in_1(reg_in_b),
.in_2(imm),
.sel(src),
.out(in_b)
);
alu alu (
.in_a(reg_in_a),
.in_b(in_b),
.func(func),
.out(out)
);
endmodule

35
rtl/module_program_counter.v Normal file
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@@ -0,0 +1,35 @@
module module_program_counter (input clock, reset,
input is_jmp, alu_not,
input [1:0] is_branch,
input [31:0] alu_out, imm,
output [31:0] addr);
wire [1:0] sel_in;
wire [31:0] pc_addr, new_addr;
mux2_1 #(2) mux2_pc_sel_branch (
.in_1(is_branch),
.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
.sel(is_jmp),
.out(sel_in)
);
mux4_1 mux4_pc_sel_in (
.in_1(pc_addr + 4),
.in_2(pc_addr + imm),
.in_3(alu_out),
.in_4(0),
.sel(sel_in),
.out(new_addr)
);
program_counter program_counter (
.clock(clock),
.reset(reset),
.new_addr(new_addr),
.pc_addr(pc_addr)
);
assign addr = pc_addr;
endmodule

30
rtl/module_registers_bank.v Normal file
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@@ -0,0 +1,30 @@
module module_registers_bank (input clock, reset, we,
input [1:0] sel_data_in,
input [4:0] sel_in, sel_out_a, sel_out_b,
input [31:0] alu_out, mem_out, pc_addr,
output [31:0] data_out_a, data_out_b);
wire [31:0] data_in;
mux4_1 mux4_reg_sel_data_in (
.in_1(alu_out),
.in_2(mem_out),
.in_3(pc_addr + 4),
.in_4(pc_addr + alu_out),
.sel(sel_data_in),
.out(data_in)
);
registers_bank registers_bank (
.clock(clock),
.reset(reset),
.we(we),
.sel_in(sel_in),
.sel_out_a(sel_out_a),
.sel_out_b(sel_out_b),
.data_in(data_in),
.data_out_a(data_out_a),
.data_out_b(data_out_b)
);
endmodule

4
rtl/program_counter.v
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@@ -1,12 +1,12 @@
module program_counter (input clock, reset,
input [31:0] pc_new_addr,
input [31:0] new_addr,
output reg [31:0] pc_addr);
always @ (posedge clock, posedge reset) begin
if (reset == 1'b1)
pc_addr <= 32'b0;
else
pc_addr <= pc_new_addr;
pc_addr <= new_addr;
end
endmodule

65
rtl/risc_v_cpu.v
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@@ -8,11 +8,11 @@ module risc_v_cpu (input clock, reset,
wire reg_we;
wire [1:0] reg_sel_data_in;
wire [4:0] reg_sel_out_a, reg_sel_out_b, reg_sel_in;
wire [31:0] reg_data_out_a, reg_data_out_b, reg_data_in;
wire [31:0] reg_data_out_a, reg_data_out_b;
wire alu_src, alu_not;
wire [3:0] alu_func;
wire [31:0] alu_in_b, alu_out;
wire [31:0] alu_out;
wire mem_we;
wire [1:0] mem_func_in;
@@ -20,8 +20,8 @@ module risc_v_cpu (input clock, reset,
wire [31:0] mem_out;
wire pc_is_jmp;
wire [1:0] pc_is_branch, pc_sel_in;
wire [31:0] pc_addr, pc_new_addr;
wire [1:0] pc_is_branch;
wire [31:0] pc_addr;
decoder decoder (
.instruction(instruction),
@@ -41,53 +41,39 @@ module risc_v_cpu (input clock, reset,
.alu_not(alu_not)
);
registers_bank registers_bank (
module_registers_bank module_registers_bank (
.clock(clock),
.reset(reset),
.we(reg_we),
.sel_data_in(reg_sel_data_in),
.sel_in(reg_sel_in),
.sel_out_a(reg_sel_out_a),
.sel_out_b(reg_sel_out_b),
.data_in(reg_data_in),
.alu_out(alu_out),
.mem_out(mem_out),
.pc_addr(pc_addr),
.data_out_a(reg_data_out_a),
.data_out_b(reg_data_out_b)
);
mux2_1 mux2_alu_in_b (
.in_1(reg_data_out_b),
.in_2(imm),
.sel(alu_src),
.out(alu_in_b)
);
alu alu (
.in_a(reg_data_out_a),
.in_b(alu_in_b),
module_alu module_alu (
.src(alu_src),
.func(alu_func),
.reg_in_a(reg_data_out_a),
.reg_in_b(reg_data_out_b),
.imm(imm),
.out(alu_out)
);
mux2_1 #(2) mux2_pc_sel_branch (
.in_1(pc_is_branch),
.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
.sel(pc_is_jmp),
.out(pc_sel_in)
);
mux4_1 mux4_pc_sel_in (
.in_1(pc_addr + 4),
.in_2(pc_addr + imm),
.in_3(alu_out),
.in_4(0),
.sel(pc_sel_in),
.out(pc_new_addr)
);
program_counter program_counter (
module_program_counter module_program_counter (
.clock(clock),
.reset(reset),
.pc_new_addr(pc_new_addr),
.pc_addr(pc_addr)
.is_jmp(pc_is_jmp),
.is_branch(pc_is_branch),
.alu_not(alu_not),
.alu_out(alu_out),
.imm(imm),
.addr(pc_addr)
);
instruction uut_instruction (
@@ -106,13 +92,4 @@ module risc_v_cpu (input clock, reset,
.data_out(mem_out)
);
mux4_1 mux4_reg_sel_data_in (
.in_1(alu_out),
.in_2(mem_out),
.in_3(pc_addr + 4),
.in_4(pc_addr + alu_out),
.sel(reg_sel_data_in),
.out(reg_data_in)
);
endmodule