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RISC-V_Verilog
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Fix: Model Sim Warning Message

This commit is contained in:
brice.boisson 2023-11-24 19:41:40 +09:00
parent ed1220978f
commit 9361c493c4
1 changed files with 7 additions and 3 deletions
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10
scripts/run_test.sh
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@ -1,6 +1,6 @@
#!/bin/sh #!/bin/sh
rm -rf work runtime_test.tmp final_test.tmp rm -rf runtime_test.tmp final_test.tmp
SCRIPT_FOLDER="./../scripts" SCRIPT_FOLDER="./../scripts"
TEST_BENCH_FOLDER="./../tb" TEST_BENCH_FOLDER="./../tb"
@ -21,6 +21,7 @@ run_test ()
{ {
TEST_FILE_PATH=$1 TEST_FILE_PATH=$1
echo
echo "$BOLD========== $TEST_BENCH - $(basename $TEST_FILE_PATH .S) ==========$NORMAL" echo "$BOLD========== $TEST_BENCH - $(basename $TEST_FILE_PATH .S) ==========$NORMAL"
if [ ! -f "$TEST_FILE_PATH" ]; then if [ ! -f "$TEST_FILE_PATH" ]; then
@ -65,8 +66,8 @@ print_result ()
elif [[ $line == *"[PASS]"* ]]; then elif [[ $line == *"[PASS]"* ]]; then
((nb_pass++)) ((nb_pass++))
((nb_test++)) ((nb_test++))
elif [[ $line == *"\*\* Warning"* ]]; then elif [[ $line == *"** Warning"* ]]; then
echo "$line" | cut -c 3- echo "$line" | cut -c 6-
fi fi
done < ./transcript done < ./transcript
@ -75,6 +76,7 @@ print_result ()
if [ -z "$TEST_FILE" ] || [ "$TEST_FILE" = "all" ]; then if [ -z "$TEST_FILE" ] || [ "$TEST_FILE" = "all" ]; then
echo
echo "$BOLD========== $TEST_BENCH - Test Bench ==========$NORMAL" echo "$BOLD========== $TEST_BENCH - Test Bench ==========$NORMAL"
./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH" ./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH"
@ -105,4 +107,6 @@ if [ ! -z "$TEST_FILE" ]; then
fi fi
fi fi
echo
exit 0 exit 0