Add: test from gcc

Makefile

@@ -14,3 +14,6 @@ clean:
 	rm -rf transcript
 	rm -rf sim/vsim.wlf
 	rm -rf sim/simu.do
+	rm -rf tb/test_source_code/**/*.bin
+	rm -rf tb/test_source_code/**/*.elf
+	rm -rf tb/test_source_code/**/*.o

rtl/decoder.v

@@ -147,7 +147,7 @@ endfunction
                 alu_not = 0;
             end
             BRANCH : begin // BRANCH - Beq, ...
-                imm[11:0] = {instruction[31:25], instruction[11:7]};
+                imm[11:0] = {instruction[7], instruction[30:25], instruction[11:8], 1'b0};
                 imm[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 20'b00000000000000000000 : 20'b11111111111111111111;
                 reg_we = 0;
                 reg_sel_data_in = 2'b00;
@@ -164,7 +164,7 @@ endfunction
                 alu_not = branch_not(instruction[14:12]);
             end
             JAL : begin // JUMP - Jal
-                imm[19:0] = instruction[31:12];
+                imm[19:0] = {instruction[31], instruction[19:12], instruction[20], instruction[30:25], instruction[24:21], 1'b0};
                 imm[31:20] = (instruction[31] == 0) ? 12'b000000000000 : 12'b111111111111;
                 reg_we = 1;
                 reg_sel_data_in = 2'b10;

rtl/risc_v_cpu.v

@@ -69,7 +69,7 @@ module risc_v_cpu (input         clock, reset,
 
     mux2_1 #(2) mux2_pc_sel_branch (
         .in_1(pc_is_branch),
-        .in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
+        .in_2({1'b0, (alu_not ? (alu_out == 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
         .sel(pc_is_jmp),
         .out(pc_sel_in)
     );

scripts/get_bin.sh

@@ -17,5 +17,7 @@ fi
 NAME=$1
 
 riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${NAME}.S -o ${NAME}.o
-riscv32-unknown-elf-ld -Ttext=0x1000 ${NAME}.o -o ${NAME}.elf
+riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf
 riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin
+
+# rm -rf ${NAME}.o ${NAME}.elf

sim/Makefile

@@ -1,4 +1,5 @@
 all:
+	./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test
 	vsim -c -do "do simu.do; quit -f"
 
 debug:

tb/tb_risc_v_cpu-dyn.v

@@ -44,6 +44,7 @@ module tb_risc_v_cpu ();
             read_instruction_2 = $fgetc(bin_file_inputs);
             read_instruction_3 = $fgetc(bin_file_inputs);
             read_instruction_4 = $fgetc(bin_file_inputs);
+            $display("read_instruction_1: %b", read_instruction_1);
 
             if (
                 read_instruction_1[8] != 1'b1 &&
@@ -51,10 +52,10 @@ module tb_risc_v_cpu ();
                 read_instruction_3[8] != 1'b1 &&
                 read_instruction_4[8] != 1'b1
             ) begin
-                risc_v_cpu.uut_instruction.memory[i]   = read_instruction_4[7:0];
+                risc_v_cpu.uut_instruction.memory[i]   = read_instruction_1[7:0];
-                risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_3[7:0];
+                risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_2[7:0];
-                risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_2[7:0];
+                risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_3[7:0];
-                risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_1[7:0];
+                risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_4[7:0];
                 i = i + 4;
             end
         end
@@ -63,7 +64,7 @@ module tb_risc_v_cpu ();
         `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[2], 8'b10000111)
         `assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[3], 8'b10110011)
 
-        for (i = 0; i < 1; i = i + 1) begin
+        for (i = 0; i < 100; i = i + 1) begin
             `next_cycle
             // run
         end