brice/RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add: named parameter for ALU func | alu test case

Browse Source
This commit is contained in:
brice.boisson
2023-10-24 10:49:29 +09:00
parent 5829400fea
commit b99914f42d
4 changed files with 135 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
rtl/alu.v
View File

@@ -2,17 +2,20 @@ module alu (input [31:0] in_a, in_b,
input [3:0] op_code,
output reg [31:0] out);
`include "alu_func.vh"
always@ (*) begin
case (op_code)
4'b0000 : out <= in_a + in_b;
4'b0001 : out <= in_a - in_b;
4'b0010 : out <= in_a << in_b;
4'b0011 : out <= (in_a < in_b) ? 1 : 0;
4'b0100 : out <= in_a ^ in_b;
4'b0101 : out <= in_a >> in_b;
4'b0111 : out <= in_a >>> in_b;
4'b1000 : out <= in_a | in_b;
4'b1001 : out <= in_a & in_b;
ADD : out <= in_a + in_b;
SUB : out <= in_a - in_b;
SLL : out <= in_a << in_b;
SLT : out <= ((in_a[31] != in_b[31]) ? in_a[31] == 1'b1 : in_a < in_b) ? 1 : 0;
SLTU : out <= (in_a < in_b) ? 1 : 0;
XOR : out <= in_a ^ in_b;
SRL : out <= in_a >> in_b;
SRA : out <= in_a >>> in_b;
OR : out <= in_a | in_b;
AND : out <= in_a & in_b;
default : out <= 32'b0;
endcase
end

10
rtl/alu_func.vh Normal file
View File

@@ -0,0 +1,10 @@
parameter [3:0] ADD = 4'b0000;
parameter [3:0] SUB = 4'b0001;
parameter [3:0] SLL = 4'b0010;
parameter [3:0] SLT = 4'b0011;
parameter [3:0] SLTU = 4'b0100;
parameter [3:0] XOR = 4'b0101;
parameter [3:0] SRL = 4'b0110;
parameter [3:0] SRA = 4'b0111;
parameter [3:0] OR = 4'b1000;
parameter [3:0] AND = 4'b1001;

35
rtl/decoder.v
View File

@@ -10,19 +10,19 @@ module decoder (input [31:0] instruction,
output reg pc_is_jmp, alu_not);
`include "op_code.vh"
`include "alu_func.vh"
function [3:0] get_alu_func(input [2:0] op_code, input arithmetic);
begin
case (op_code)
3'b000 : get_alu_func = arithmetic ? 4'b0001 : 4'b0000;
3'b001 : get_alu_func = 4'b0010;
3'b010 : get_alu_func = 4'b0011;
3'b011 : get_alu_func = 4'b0011;
3'b100 : get_alu_func = 4'b0100;
3'b101 : get_alu_func = arithmetic ? 4'b0111 : 4'b0101;
3'b110 : get_alu_func = 4'b1000;
3'b111 : get_alu_func = 4'b1010;
3'b111 : get_alu_func = 4'b1011;
3'b000 : get_alu_func = arithmetic ? SUB : ADD;
3'b001 : get_alu_func = SLL;
3'b010 : get_alu_func = SLT;
3'b011 : get_alu_func = SLTU;
3'b100 : get_alu_func = XOR;
3'b101 : get_alu_func = arithmetic ? SRA : SRL;
3'b110 : get_alu_func = OR;
3'b111 : get_alu_func = AND;
default : get_alu_func= 4'b0000;
endcase
end
@@ -31,15 +31,14 @@ endfunction
function [3:0] get_alu_func_imm(input [2:0] op_code, input arithmetic);
begin
case (op_code)
3'b000 : get_alu_func_imm = 4'b0000;
3'b001 : get_alu_func_imm = 4'b0010;
3'b010 : get_alu_func_imm = 4'b0011;
3'b011 : get_alu_func_imm = 4'b0100;
3'b100 : get_alu_func_imm = 4'b0101;
3'b101 : get_alu_func_imm = arithmetic ? 4'b1000 : 4'b0111;
3'b110 : get_alu_func_imm = 4'b1001;
3'b111 : get_alu_func_imm = 4'b1010;
3'b111 : get_alu_func_imm = 4'b1011;
3'b000 : get_alu_func_imm = ADD;
3'b001 : get_alu_func_imm = SLL;
3'b010 : get_alu_func_imm = SLT;
3'b011 : get_alu_func_imm = SLTU;
3'b100 : get_alu_func_imm = XOR;
3'b101 : get_alu_func_imm = arithmetic ? SRA : SRL;
3'b110 : get_alu_func_imm = OR;
3'b111 : get_alu_func_imm = AND;
default : get_alu_func_imm = 4'b0000;
endcase
end