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Rework: separate each step of the pipeline in a different component

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BOISSON Brice
2023-12-04 11:34:39 +09:00
committed by GitHub
parent ffa137da41
commit ca6398d1e1
8 changed files with 179 additions and 115 deletions
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8
tb/tb_risc_v_cpu-dyn.v
View File

@@ -112,8 +112,8 @@ module tb_risc_v_cpu ();
/* Run The Program */
for (i = 0; i < 10000; i = i + 1) begin
if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
if (test[risc_v_cpu.module_program_counter.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
curent_addr = risc_v_cpu.module_program_counter.program_counter.pc_addr / 4;
`next_cycle
/* Test State During Execution */
@@ -151,9 +151,9 @@ module tb_risc_v_cpu ();
/* Test State After Execution */
if (reg_number < 6'b100000) begin
`assert_no_wait_reg("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.registers_bank.registers[reg_number[4:0]])
`assert_no_wait_reg("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.module_registers_bank.registers_bank.registers[reg_number[4:0]])
end else if (reg_number == 6'b100000) begin
`assert_no_wait_pc("FINAL", 1'bx, reg_test_value, risc_v_cpu.program_counter.pc_addr)
`assert_no_wait_pc("FINAL", 1'bx, reg_test_value, risc_v_cpu.module_program_counter.program_counter.pc_addr)
end else if (reg_number > 6'b100000) begin
`assert_no_wait_mem("FINAL", 1'bx, reg_number - 6'b100001, reg_test_value, {risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4 + 3], risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4 + 2], risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4 + 1], risc_v_cpu.memory.memory[(test[curent_addr][5:0] - 6'b100001) * 4]})
end

126
tb/tb_risc_v_cpu.v
View File

@@ -66,117 +66,117 @@ module tb_risc_v_cpu ();
risc_v_cpu.uut_instruction.memory[23] = 8'b11111111;
`next_cycle
`assert_no_wait("FIBO INIT: ADDi $1, R[0], R[6] - R[6] = 1", risc_v_cpu.registers_bank.registers[6], 1)
`assert_no_wait("FIBO INIT: ADDi $1, R[0], R[6] - R[6] = 1", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 1)
`next_cycle
`assert_no_wait("FIBO INIT: ADDi $0, R[0], R[7] - R[7] = 0", risc_v_cpu.registers_bank.registers[7], 0)
`assert_no_wait("FIBO INIT: ADDi $0, R[0], R[7] - R[7] = 0", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 0)
`next_cycle
`assert_no_wait("FIBO CYCLE 1: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 1)
`assert_no_wait("FIBO CYCLE 1: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 1)
`next_cycle
`assert_no_wait("FIBO CYCLE 1: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 1)
`assert_no_wait("FIBO CYCLE 1: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 1)
`next_cycle
`assert_no_wait("FIBO CYCLE 1: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 1)
`assert_no_wait("FIBO CYCLE 1: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1)
`next_cycle
`assert_no_wait("FIBO VALUE 1: 1", risc_v_cpu.registers_bank.registers[7], 1)
`assert_no_wait("FIBO CYCLE 1: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 1: 1", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1)
`assert_no_wait("FIBO CYCLE 1: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 2: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 1)
`assert_no_wait("FIBO CYCLE 2: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 1)
`next_cycle
`assert_no_wait("FIBO CYCLE 2: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 2)
`assert_no_wait("FIBO CYCLE 2: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 2)
`next_cycle
`assert_no_wait("FIBO CYCLE 2: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 1)
`assert_no_wait("FIBO CYCLE 2: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1)
`next_cycle
`assert_no_wait("FIBO VALUE 2: 1", risc_v_cpu.registers_bank.registers[7], 1)
`assert_no_wait("FIBO CYCLE 2: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 2: 1", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 1)
`assert_no_wait("FIBO CYCLE 2: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 3: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 2)
`assert_no_wait("FIBO CYCLE 3: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 2)
`next_cycle
`assert_no_wait("FIBO CYCLE 3: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 3)
`assert_no_wait("FIBO CYCLE 3: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 3)
`next_cycle
`assert_no_wait("FIBO CYCLE 3: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 2)
`assert_no_wait("FIBO CYCLE 3: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 2)
`next_cycle
`assert_no_wait("FIBO VALUE 3: 2", risc_v_cpu.registers_bank.registers[7], 2)
`assert_no_wait("FIBO CYCLE 3: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 3: 2", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 2)
`assert_no_wait("FIBO CYCLE 3: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 4: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 3)
`assert_no_wait("FIBO CYCLE 4: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 3)
`next_cycle
`assert_no_wait("FIBO CYCLE 4: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 5)
`assert_no_wait("FIBO CYCLE 4: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 5)
`next_cycle
`assert_no_wait("FIBO CYCLE 4: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 3)
`assert_no_wait("FIBO CYCLE 4: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 3)
`next_cycle
`assert_no_wait("FIBO VALUE 4: 3", risc_v_cpu.registers_bank.registers[7], 3)
`assert_no_wait("FIBO CYCLE 4: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 4: 3", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 3)
`assert_no_wait("FIBO CYCLE 4: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 5: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 5)
`assert_no_wait("FIBO CYCLE 5: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 5)
`next_cycle
`assert_no_wait("FIBO CYCLE 5: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 8)
`assert_no_wait("FIBO CYCLE 5: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 5: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 5)
`assert_no_wait("FIBO CYCLE 5: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 5)
`next_cycle
`assert_no_wait("FIBO VALUE 5: 5", risc_v_cpu.registers_bank.registers[7], 5)
`assert_no_wait("FIBO CYCLE 5: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 5: 5", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 5)
`assert_no_wait("FIBO CYCLE 5: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 6: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 8)
`assert_no_wait("FIBO CYCLE 6: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 6: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 13)
`assert_no_wait("FIBO CYCLE 6: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 13)
`next_cycle
`assert_no_wait("FIBO CYCLE 6: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 8)
`assert_no_wait("FIBO CYCLE 6: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 8)
`next_cycle
`assert_no_wait("FIBO VALUE 6: 8", risc_v_cpu.registers_bank.registers[7], 8)
`assert_no_wait("FIBO CYCLE 6: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 6: 8", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 8)
`assert_no_wait("FIBO CYCLE 6: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 7: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 13)
`assert_no_wait("FIBO CYCLE 7: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 13)
`next_cycle
`assert_no_wait("FIBO CYCLE 7: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 21)
`assert_no_wait("FIBO CYCLE 7: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 21)
`next_cycle
`assert_no_wait("FIBO CYCLE 7: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 13)
`assert_no_wait("FIBO CYCLE 7: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 13)
`next_cycle
`assert_no_wait("FIBO VALUE 7: 13", risc_v_cpu.registers_bank.registers[7], 13)
`assert_no_wait("FIBO CYCLE 7: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 7: 13", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 13)
`assert_no_wait("FIBO CYCLE 7: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 8: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 21)
`assert_no_wait("FIBO CYCLE 8: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 21)
`next_cycle
`assert_no_wait("FIBO CYCLE 8: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 34)
`assert_no_wait("FIBO CYCLE 8: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 34)
`next_cycle
`assert_no_wait("FIBO CYCLE 8: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 21)
`assert_no_wait("FIBO CYCLE 8: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 21)
`next_cycle
`assert_no_wait("FIBO VALUE 8: 21", risc_v_cpu.registers_bank.registers[7], 21)
`assert_no_wait("FIBO CYCLE 8: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 8: 21", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 21)
`assert_no_wait("FIBO CYCLE 8: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 9: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 34)
`assert_no_wait("FIBO CYCLE 9: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 34)
`next_cycle
`assert_no_wait("FIBO CYCLE 9: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 55)
`assert_no_wait("FIBO CYCLE 9: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 55)
`next_cycle
`assert_no_wait("FIBO CYCLE 9: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 34)
`assert_no_wait("FIBO CYCLE 9: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 34)
`next_cycle
`assert_no_wait("FIBO VALUE 9: 34", risc_v_cpu.registers_bank.registers[7], 34)
`assert_no_wait("FIBO CYCLE 9: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 9: 34", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 34)
`assert_no_wait("FIBO CYCLE 9: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 10: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 55)
`assert_no_wait("FIBO CYCLE 10: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 55)
`next_cycle
`assert_no_wait("FIBO CYCLE 10: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 89)
`assert_no_wait("FIBO CYCLE 10: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 89)
`next_cycle
`assert_no_wait("FIBO CYCLE 10: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 55)
`assert_no_wait("FIBO CYCLE 10: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 55)
`next_cycle
`assert_no_wait("FIBO VALUE 10: 55", risc_v_cpu.registers_bank.registers[7], 55)
`assert_no_wait("FIBO CYCLE 10: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 10: 55", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 55)
`assert_no_wait("FIBO CYCLE 10: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 11: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 89)
`assert_no_wait("FIBO CYCLE 11: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 89)
`next_cycle
`assert_no_wait("FIBO CYCLE 11: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 144)
`assert_no_wait("FIBO CYCLE 11: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 144)
`next_cycle
`assert_no_wait("FIBO CYCLE 11: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 89)
`assert_no_wait("FIBO CYCLE 11: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 89)
`next_cycle
`assert_no_wait("FIBO VALUE 11: 89", risc_v_cpu.registers_bank.registers[7], 89)
`assert_no_wait("FIBO CYCLE 11: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 11: 89", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 89)
`assert_no_wait("FIBO CYCLE 11: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
`next_cycle
`assert_no_wait("FIBO CYCLE 12: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.registers_bank.registers[8], 144)
`assert_no_wait("FIBO CYCLE 12: ADDi $0, R[6], R[8] - R[8] = R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[8], 144)
`next_cycle
`assert_no_wait("FIBO CYCLE 12: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.registers_bank.registers[6], 233)
`assert_no_wait("FIBO CYCLE 12: ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]", risc_v_cpu.module_registers_bank.registers_bank.registers[6], 233)
`next_cycle
`assert_no_wait("FIBO CYCLE 12: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.registers_bank.registers[7], 144)
`assert_no_wait("FIBO CYCLE 12: ADDi $0, R[8], R[7] - R[7] = R[8]", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 144)
`next_cycle
`assert_no_wait("FIBO VALUE 12: 144", risc_v_cpu.registers_bank.registers[7], 144)
`assert_no_wait("FIBO CYCLE 12: JUMP - 12", risc_v_cpu.program_counter.pc_addr, 8)
`assert_no_wait("FIBO VALUE 12: 144", risc_v_cpu.module_registers_bank.registers_bank.registers[7], 144)
`assert_no_wait("FIBO CYCLE 12: JUMP - 12", risc_v_cpu.module_program_counter.program_counter.pc_addr, 8)
/* Reset */
reset = 1'b1;
@@ -339,7 +339,7 @@ module tb_risc_v_cpu ();
`assert_no_wait("BUBBLE SORT - MEM[7]: 8", risc_v_cpu.memory.memory[7], 8)
`assert_no_wait("BUBBLE SORT - MEM[8]: 9", risc_v_cpu.memory.memory[8], 9)
`assert_no_wait("BUBBLE SORT - MEM[9]: 10", risc_v_cpu.memory.memory[9], 10)
`assert_no_wait("BUBBLE SORT - PROGRAM EXITED - PC: 76", risc_v_cpu.program_counter.pc_addr, 76)
`assert_no_wait("BUBBLE SORT - PROGRAM EXITED - PC: 76", risc_v_cpu.module_program_counter.program_counter.pc_addr, 76)
`end_message
end

4
tb/tb_tools.vh
View File

@@ -31,9 +31,9 @@
`define test_result(message, curent_addr, addr_range, test_range) \
if (test[curent_addr][addr_range:addr_range - 5] < 6'b100000) begin \
`assert_no_wait_reg(message, curent_addr, test[curent_addr][addr_range:addr_range - 5], test[curent_addr][test_range:test_range - 31], risc_v_cpu.registers_bank.registers[test[curent_addr][addr_range - 1:addr_range - 5]]) \
`assert_no_wait_reg(message, curent_addr, test[curent_addr][addr_range:addr_range - 5], test[curent_addr][test_range:test_range - 31], risc_v_cpu.module_registers_bank.registers_bank.registers[test[curent_addr][addr_range - 1:addr_range - 5]]) \
end else if (test[curent_addr][addr_range:addr_range - 5] == 6'b100000) begin \
`assert_no_wait_pc(message, curent_addr, test[curent_addr][test_range:test_range - 31], risc_v_cpu.program_counter.pc_addr) \
`assert_no_wait_pc(message, curent_addr, test[curent_addr][test_range:test_range - 31], risc_v_cpu.module_program_counter.program_counter.pc_addr) \
end else if (test[curent_addr][addr_range:addr_range - 5] > 6'b100000) begin \
`assert_no_wait_mem(message, curent_addr, test[curent_addr][addr_range:addr_range - 5] - 6'b100001, test[curent_addr][test_range:test_range - 31], {risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4 + 3], risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4 + 2], risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4 + 1], risc_v_cpu.memory.memory[(test[curent_addr][addr_range:addr_range - 5] - 6'b100001) * 4]}) \
end