brice/RISC-V_Verilog
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Fix: divide by 4 on entry test too

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brice.boisson
2023-11-25 19:38:14 +09:00
parent c6292d3b4f
commit ca6d23450d
1 changed files with 1 additions and 1 deletions
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tb/tb_risc_v_cpu-dyn.v
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@@ -112,7 +112,7 @@ module tb_risc_v_cpu ();
/* Run The Program */
for (i = 0; i < 100; i = i + 1) begin
if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin
if (test[risc_v_cpu.program_counter.pc_addr / 4][5:0] != 6'b111111) begin
curent_addr = risc_v_cpu.program_counter.pc_addr / 4;
`next_cycle
if (test[curent_addr][5:0] != 6'b111111) begin