brice/RISC-V_Verilog
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Add: generate file on make

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brice.boisson
2023-11-21 18:45:25 +09:00
parent 7d60960831
commit e2ca11548c
5 changed files with 12 additions and 10 deletions
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sim/Makefile
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@@ -1,5 +1,6 @@
all:
./../scripts/get_bin.sh ../tb/test_source_code/tb_riscv_cpu/test
python3 ./../scripts/gen_test.py ../tb/test_source_code/tb_riscv_cpu test.S
vsim -c -do "do simu.do; quit -f"
debug: