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brice:test-reg_bank-fix-1
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brice:main
brice:test-add-module_program_counter
brice:test-reg_bank-fix-1

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main ... test-reg_b

Author SHA1 Message Date
brice.boisson 292eaf842a Fix: tb reg bank delay first test after end of reset 2023-12-05 13:53:43 +09:00
1 changed files with 0 additions and 59 deletions
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tb/tb_module_program_counter.v
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@ -1,59 +0,0 @@
`timescale 1ns / 1ps
`include "tb_tools.vh"
module tb_module_program_counter ();
reg clk;
reg reset;
reg is_jmp;
reg alu_not;
reg [1:0] is_branch;
reg [31:0] alu_out;
reg [31:0] imm;
wire [31:0] addr;
integer i;
module_program_counter module_program_counter (
.clock(clk),
.reset(reset),
.is_jmp(is_jmp),
.alu_not(alu_not),
.is_branch(is_branch),
.alu_out(alu_out),
.imm(imm),
.addr(addr)
);
initial begin
clk = 1'b0;
for (i = 0; i < 100; i = i + 1) begin
#1 clk = ~clk;
end
end
initial begin
reset = 1'b1;
is_jmp = 1'b0;
alu_not = 1'b0;
is_branch = 2'b00;
alu_out = 32'b0;
imm = 32'b0;
#10
reset = 1'b0;
`assert_no_wait("module_program_counter is_jmp: 0, is_branch: 0, alu_not: 0, alu_out: 0, imm: 0", addr, 0)
<<<<<<< HEAD
#2
`assert_no_wait("module_program_counter is_jmp: 0, is_branch: 0, alu_not: 0, alu_out: 0, imm: 0", addr, 4)
#2
`assert_no_wait("module_program_counter is_jmp: 0, is_branch: 0, alu_not: 0, alu_out: 0, imm: 0", addr, 8)
=======
>>>>>>> d6f7fb498b1347201d1c08f9c368aff27a10a77f
`end_message
end
endmodule : tb_module_program_counter