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Fix: memory addressing 32 to 8 bits #2

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BriceBoisson merged 1 commits from risc-v into main 2023-10-24 12:53:08 +00:00
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BriceBoisson commented 2023-10-24 12:52:59 +00:00 (Migrated from github.com)
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Reference: brice/RISC-V_Verilog#2
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