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RISC-V_Verilog
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RISC-V base implementation #1

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BriceBoisson merged 17 commits from risc-v into main 2023-10-24 12:20:46 +00:00
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2 changed files with 22 additions and 11 deletions
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24
rtl/decoder.v
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@ -9,6 +9,8 @@ module decoder (input [31:0] instruction,
output reg [1:0] jmp_pc, output reg [1:0] jmp_pc,
output reg b_pc, alu_not); output reg b_pc, alu_not);
`include "op_code.vh"
function [3:0] get_op_code_alu(input [2:0] op_code, input arithmetic); function [3:0] get_op_code_alu(input [2:0] op_code, input arithmetic);
begin begin
case (op_code) case (op_code)
@ -76,7 +78,7 @@ endfunction
always @(*) begin always @(*) begin
case (instruction[6:2]) case (instruction[6:2])
5'b01100 : begin // OP - Add, ... OP : begin // OP - Add, ...
immediate = 0; immediate = 0;
we_reg = 1; we_reg = 1;
adder_pc = 0; adder_pc = 0;
@ -91,7 +93,7 @@ endfunction
b_pc = 0; b_pc = 0;
alu_not = 0; alu_not = 0;
end end
5'b00100 : begin // OP-IMM - Addi, ... OP_IMM : begin // OP-IMM - Addi, ...
immediate[11:0] = instruction[31:20]; immediate[11:0] = instruction[31:20];
immediate[31:12] = (instruction[14:12] == 3'b011 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111; immediate[31:12] = (instruction[14:12] == 3'b011 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
we_reg = 1; we_reg = 1;
@ -107,7 +109,7 @@ endfunction
b_pc = 0; b_pc = 0;
alu_not = 0; alu_not = 0;
end end
5'b00000 : begin // LOAD - Lw, ... LOAD : begin // LOAD - Lw, ...
immediate[11:0] = instruction[31:20]; immediate[11:0] = instruction[31:20];
immediate[31:12] = (instruction[14:12] == 3'b100 || instruction[14:12] == 3'b101 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111; immediate[31:12] = (instruction[14:12] == 3'b100 || instruction[14:12] == 3'b101 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
we_reg = 1; we_reg = 1;
@ -123,7 +125,7 @@ endfunction
b_pc = 0; b_pc = 0;
alu_not = 0; alu_not = 0;
end end
5'b01000 : begin // STORE - Sw, ... STORE : begin // STORE - Sw, ...
immediate[11:0] = {instruction[31:25], instruction[11:7]}; immediate[11:0] = {instruction[31:25], instruction[11:7]};
immediate[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111; immediate[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
we_reg = 0; we_reg = 0;
@ -139,7 +141,7 @@ endfunction
b_pc = 0; b_pc = 0;
alu_not = 0; alu_not = 0;
end end
5'b11000 : begin // BRANCH - Beq, ... BRANCH : begin // BRANCH - Beq, ...
immediate[11:0] = {instruction[31:25], instruction[11:7]}; immediate[11:0] = {instruction[31:25], instruction[11:7]};
immediate[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111; immediate[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
we_reg = 0; we_reg = 0;
@ -155,7 +157,7 @@ endfunction
b_pc = 1; b_pc = 1;
alu_not = branch_not(instruction[14:12]); alu_not = branch_not(instruction[14:12]);
end end
5'b11011 : begin // JUMP - Jal JAL : begin // JUMP - Jal
immediate[19:0] = instruction[31:12]; immediate[19:0] = instruction[31:12];
immediate[31:20] = (instruction[31] == 0) ? 12'b000000000000 : 12'b111111111111; immediate[31:20] = (instruction[31] == 0) ? 12'b000000000000 : 12'b111111111111;
we_reg = 1; we_reg = 1;
@ -171,9 +173,9 @@ endfunction
b_pc = 0; b_pc = 0;
alu_not = 0; alu_not = 0;
end end
5'b11001 : begin // JUMP REG - Jalr JALR : begin // JUMP REG - Jalr
immediate[19:0] = instruction[31:12]; immediate[11:0] = instruction[31:20];
immediate[31:20] = (instruction[31] == 0) ? 12'b000000000000 : 12'b111111111111; immediate[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
we_reg = 1; we_reg = 1;
adder_pc = 0; adder_pc = 0;
input_reg = 2'b00; input_reg = 2'b00;
@ -187,7 +189,7 @@ endfunction
b_pc = 0; b_pc = 0;
alu_not = 0; alu_not = 0;
end end
5'b01101 : begin // LUI - lui LUI : begin // LUI - lui
immediate = {instruction[31:12] << 12, 12'b000000000000}; immediate = {instruction[31:12] << 12, 12'b000000000000};
we_reg = 1; we_reg = 1;
adder_pc = 0; adder_pc = 0;
@ -202,7 +204,7 @@ endfunction
b_pc = 0; b_pc = 0;
alu_not = 0; alu_not = 0;
end end
5'b00101 : begin // AUIPC - auipc AUIPC : begin // AUIPC - auipc
immediate = {instruction[31:12] << 12, 12'b000000000000}; immediate = {instruction[31:12] << 12, 12'b000000000000};
we_reg = 1; we_reg = 1;
adder_pc = 1; adder_pc = 1;

9
rtl/op_code.vh Normal file
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@ -0,0 +1,9 @@
parameter [4:0] OP = 5'b01100;
parameter [4:0] OP_IMM = 5'b00100;
parameter [4:0] LOAD = 5'b00000;
parameter [4:0] STORE = 5'b01000;
parameter [4:0] BRANCH = 5'b11000;
parameter [4:0] JAL = 5'b11011;
parameter [4:0] JALR = 5'b11001;
parameter [4:0] LUI = 5'b01101;
parameter [4:0] AUIPC = 5'b00101;